resume - University of California, Santa Cruz

Riadul Islam
Phone: +1(831)419-8272, Email: [email protected]
Seeking a summer-internship in the area of Design Automation of VLSI, CAD, and related areas.
Education
1. Ph.D. Candidate, Computer Engineering, [09/2012–Present].
University of California, Santa Cruz, USA, Expected Graduation: Fall 2016.
Topic: Low-Power Clock Network Design & Optimization.
2. Master of Applied Science, Electrical and Computer Engineering, [09/2009–08/2011].
Concordia University, Montreal, Quebec, Canada, CGPA: 4.15 out of 4.3.
Graduate Project: 64-bit pipeline adder using Synopsys IC compiler with TSMC 65nm technology library.
Thesis: High-speed Energy-efficient Soft Error Tolerant Flip-flops; Supervisor: Dr. S. M. Jahinuzzaman.
3. Bachelor of Science, Electrical and Electronic Engineering, [04/2002–06/2007].
Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh, CGPA: 3.55 out of 4.0.
Relevant Graduate Coursework
Advanced VLSI (CMPE 222), Digital System Design and Synthesis (COEN 6501), ASIC Design (COEN 6511),
Computer Architecture (CMPE 202), CMOS RF Circuit Design (EE 226), Analysis of Algorithms (CMPS 201).
Working Experience
1. Design Automation Engineer, VLSI-DA Lab, UCSC, California, USA, [09/2012–Present].
Responsibility: Developing an automated tool for clock routing, optimization using novel current-mode flip-flop.
2. Teaching Assistant, Course: Computer Architecture (CMPE110), UCSC, California, USA, [W’13, F’14].
Responsibility: Conducting sections, defining homeworks, office hours, grading.
3. Research Internship at ISR Technologies, Montreal, Quebec, Canada, [05/2012–08/2012].
Responsibility: FPGA based fault measurement using MATLAB, C, and vhdl code.
4. Worked as a Lecturer in the Dep. of EEE of The University of Asia Pacific, Dhaka, Bangladesh, [10/2007–
08/2009].
Instructed: VLSI-I, Electronics-I.
Summary of Skills
1. Computer Language and Tools: C++, Python, Verilog, Latex, Git, SVN, Vim, Unix, MIPS, HTML,
Cadence Virtuoso, MATLAB, Synopsys VHDL system simulator, Xilinx ISE, HSpice.
List of Publications
1. R. Islam and M. Guthaus, ‘Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop,’
submitted to IEEE TCAS-I.
2. P. Lin, H. Fahmy, R. Islam and M. Guthaus, ‘LC Resonant Clock Resource Minimization using Compensation
Capacitance,’ submitted to IEEE ISCAS 2015.
3. H. Fahmy, P. Lin, R. Islam and M. Guthaus, ‘Switched Capacitor Quasi Adiabatic Clock,’ submitted to
IEEE ISCAS 2015.
4. R. Islam and M. Guthaus, ‘Current-Mode Clock Distribution,’ in IEEE ISCAS, Mel., Australia, June 1–5,
2014.
5. S. E. Esmaeili, R. Islam, A. J. Al-khalili, and G. E. R. Cowan, ‘Dual-Edge Triggered Sense Amplifier Flipflop Utilizing an Improved Scheme to Reduce Area, Power, and Complexity,’ in IEEE ICECS, Seville, Spain,
December 09–12, 2012.
6. R. Islam, ‘A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop,’ in Proc.
ISQED, CA, USA, March 19–21, 2012.
7. R. Islam, S. E. Esmaeili, and T. Islam, ‘A High Performance Clocked Precharge SEU Hardened Flip-flop,’
in IEEE ASICON, Xiamen, China, October 25-28, 2011.
8. S. M. Jahinuzzaman and R. Islam, ‘TSPC-DICE: A Single Phase Clock High Performance SEU Hardened
Flip-Flop,’ in IEEE MWSCAS, Seattle, WA, August 1-4, 2010.

Download Report