Ain Shams University Faculty of Engineering EECE Dept. ECE 342: Digital Circuits Fall 2014 Dr. Sameh A. Ibrahim Assignment 4 Sequential Logic 1. Both circuits in Fig. 1 behave as latch. a. Is it positive or negative latch? b. Which one is more reliable (robust)? Why? c. How can you calculate the set-up time tsu in both cases? (a) (b) Fig. 1 2. An alternative circuit to implement a master-slave register is shown in Fig. 2. a. Is it positive or negative edge-triggered register? b. Inverters I2 and I4 are called level-restoring devices. Can you tell why? c. Is it possible to use simple NMOS pass transistor instead of the CMOS transmission gate? d. Why I2 and I4 should be weak inverters (small sized transistors)? e. What if we eliminate level-restoring inverters? 3. Design a pipelined circuit of the function F = (AB+BC) + D. Use C 2MOS latches for the implementation. Draw the schematics of the circuit assuming you are allowed to introduce two pipeline stages between the input and the output. Try both static and dynamic implementation of the logic. Place the latches so that a maximum clock speed is obtained. What limits clock speed in both cases? Page 1 of 3 Ain Shams University Faculty of Engineering EECE Dept. ECE 342: Digital Circuits Fall 2014 Dr. Sameh A. Ibrahim ̅̅̅̅ + BF ̅̅̅̅̅n ) + C with as many stages as possible. Include 4. Pipeline the function Fn+1 = (AB the input and output latches. a. Design it at the gate level. Estimate the minimum clock period in terms of gate delays. Under what conditions can a race occur, assuming fast clock rise and fall times. b. Sketch the transistor schematics using basic TSPC latches. c. Sketch the schematics using TSPC latches with logic integrated into the latches. d. Discuss the pros and cons of the latter approach. Fig. 2 5. [2012] a. For the latch circuit shown in Fig. 3, label the boxes 𝐷, 𝐶𝐿𝐾, ̅̅̅̅̅̅ 𝐶𝐿𝐾 , 𝑄̅ such that the circuit works as a positive transparent inverting latch. b. Is the circuit in Fig. 3 a static or a dynamic latch? Justify your answer. c. Suppose the latch is used as the slave stage of an edge-triggered flip-flop and that node 1 and node 2 in Fig. 5 are initially at 1.8 V and 0 V, respectively. Assuming Rp = 300 Ω for a PMOS device with W/L = 1/1, Rn = 100 Ω for an NMOS device with W/L = 1/1, CA = 19 fF, CB = 23 fF, C1 = 150 fF, and tpHL for the inverter is 8.9 ps, estimate the clock-to-Q delay for the latch using the switch RC model for the transistors. Hint 1: Switch model propagation delay times are tpHL or tpLH = 0.69RCL. Hint 2: Note the capacitor voltage variation to estimate the load capacitance. Fig. 3 Page 2 of 3 Ain Shams University Faculty of Engineering EECE Dept. ECE 342: Digital Circuits Fall 2014 Dr. Sameh A. Ibrahim 6. [2013] The circuit shown in Fig. 4 has the following parameters for the components: Clock period = 90 nS with a 50% duty cycle. For registers R1 and R2: tcq = 40 nS, tsu = 20 nS and thold = 45 nS AND gate delay = 15 nS OR gate delay = 20 nS Inverter delay = 5 nS a. Will this circuit work correctly? Explain, and find the magnitude of the violation, if any. b. If you cannot move any cells, but can add inverters anywhere in the design, show the new design which fixes the violation but does not change the functionality. c. If the design above has already been implemented in Silicon, you cannot change the design or add circuitry. Is there still a way to make the circuit work? Explain. Fig. 4 7. Page 3 of 3