New Modular High Voltage LDMOS Technology Based on Deep

New Modular High Voltage LDMOS Technology
Based on Deep Trench Isolation and 0.18um CMOS
Platform
Moshe Agam, Thierry Yao, Agajan Suwhanov, Tracy Myers, Yutaka Ota, Sallie Hose, Matt Comard
ON Semiconductor, Gresham, OR, USA ([email protected], [email protected])
epitaxial layer (N-epi) is grown on a P+ substrate, followed by
a highly doped N-type buried layer (BLN). On top of this stack
a P-type epitaxial layer (P-epi) is grown. Each layer’s thickness
and resistivity is optimized to reduce parasitic BJT gain and
maintain sufficient breakdown voltage between BLN and P-epi
and between pockets which are isolated by DTI.
Abstract—This paper presents the challenges of integrating
70V and 45V lateral DMOS transistor modules into a 0.18um
base line process. This integration is achieved with minimal
impact on baseline process and circuit IP’s. Multi-epitaxial stack
and Deep Trench Isolation (DTI) modules assure up to 140V
isolation capability between different areas in the chip.
Keywords—high power, LDMOS, DTI, deep trench, multi layer
epitaxial, dislocations, stress, proximity
I.
B. DTI formation
DTI is etched 40um into the silicon after the epi stack is
grown. The trench is etched in a two-step process. The first
step is to etch a trench 11um deep. A phosphorous- rich film is
then deposited in the trench. We then performed an anneal to
drive the phosphorus into the silicon sidewalls of the trench,
which creates N-sinker. This N-doped layer provides the
connection to the buried N layer (BLN). Following the
formation of this N-sinker, the trench is then etched to the final
depth. A high-quality thermal oxide is grown along the trench
walls, and deposited oxide is then added. This oxide stack
defines the DTI dielectric. The trench is then filled with a poly
silicon stress relief layer. All of the epi and DTI construction is
done prior to the standard CMOS processing to minimize the
impact on the baseline devices.
INTRODUCTION
Integrated high power IC’s are largely intended for the
automotive industry in areas of reduced emissions and fuel
economy; advanced drive assistance systems; the enhancement
of vehicle personalization and comfort, etc. High power IC’s
are also used for medical applications such as ultrasound
imaging and advanced power management controllers.
A modular integration of high power devices with a
foundry-compatible base line process has many advantages in
terms of cost and design effectiveness. This integrative
approach allows high density logic design, side by side with
customized high power circuits.
In order to achieve such integration, it is necessary to
assign voltage marks to different areas in the chip and provide
appropriate isolation between high and low voltage regions.
This isolation is achieved by constructing a stacked multi-layer
epitaxial substrate and by adding a modular DTI (Deep Trench
Isolation) feature. This does assure up to a 140v potential
difference between isolated pockets in the chip. This paper
will discuss the integration of the high-power devices in a
CMOS baseline process while addressing the challenges of this
approach, and will present an overview of the construction of
these high power devices.
II.
ISOLATION MODULES
A. EPI and BLN modules
Process integration and device architecture require a stack
of multi-layer epitaxial growth on a P+ substrate to support
critical high voltage and power requirements. An N-type
978-1-4799-3944-2/14/$31.00 ©2014 IEEE
Figure 1 - Cross section of EPI layers, DTI, and N-sinker.
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There are several aspects of the N-sinker and DTI dielectric
formation which are important for the physical and electrical
properties of the DTI isolation.
Vpoly
0V
DTI Vbd
The N-sinker must be doped sufficiently high to provide a
relatively low-resistance contact to the BLN. To determine the
necessary resistance and lateral diffusion, tests were performed
and evaluated based on the phosphorus concentration and
anneal temperature, as shown in Figure 2.
Top P-epi
50
40
30
20
VP-substrate
10
Figure 4 - Measurement of DTI breakdown voltage
5.0%
7.0%
9.0%
3.5%
5.0%
950
7.0%
9.0%
1050
C. Defect study
During development, crystal dislocations were observed.
Dislocation loops were found around the BLN arsenic
implanted area. Studies showed that the cause of this
dislocation was due to an excess of arsenic in the BLN layer
which resulted in lattice mismatch. After DTI etch and Nsinker formation, these dislocation loops propagated outside of
the BLN layer and aligned in a 45 degree direction from the
trench bottom corner. Because the dislocation is related to the
mechanical stress, it has pattern density dependency.
Figure 2 - Resistance of N-sinker with different phosphorus doping
(%) concentrations and anneal conditions (950°C and 1050°C).
In addition, tests were performed regarding the DTI
dielectric thickness that defines the coupling capacitance
between adjacent pockets. The pocket breakdown voltage is
dependent on this coupling capacitance. Figure 3 shows the
dependence of breakdown voltage on the dielectric thickness.
200
Figure 5 shows a cross-sectional TEM picture of crystal
defect generated by the high dose BLN implant step. Figure 6
shows cross-sectional SEM pictures after first DTI etch.
Maximum BLN dose was determined to prevent the generation
of crystal defects at minimum design rule patterns.
190
Pocket Breakdown
Voltage
180
170
160
150
140
130
120
110
100
1.2
1.3
1.4
1.5
1.6
BLN
DTI Oxide Thickness(um)
Figure 3 - Pocket breakdown voltage on DTI dielectric thickness.
The ratio between the thermal and deposited oxide process
is also important, as thick thermal oxide puts stress on the
wafer causing the wafer to bow. Too little thermal oxidation
creates stress induced defects in the silicon. The ratio of
thermal oxide to deposited oxide was optimized taking these
factors into consideration.
Figure 5 -Cross sectional TEM picture after P-epi and thermal
treatment for high dose BLN.
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Base line CMOS LDD, and well and Vt adjust implants were
used to construct the source side of the transistor.
Figure 8 shows the layout parameters which were
considered to optimize the device operation. (1) Lg: overlap
of the well implant and the poly gate from the source side. (2)
Lacc: the overlap of the drain implant and the poly gate from
the drain side. (3) Lepi: the space between the drain and
source implants. (4) Lsti: the field distance between the
isolated drain and the transistor drain edge. (5) Lpov: Poly
overlap of field in the drain side. Figure 8 shows a cross
section of NLDMOS device.
Lg is optimized for low leakage and threshold voltage
requirements. Lacc and Lepi are optimized to distance the
drain current flow away from the STI interface, in order to
reduce the probability of trap formation. Lsti and Lpov are
optimized to achieve the operating voltage requirement with
minimal impact on RDSON.
Figure 6 –Cross-sectional SEM after N-Sinker formation. (a) BLN,
high doping (b) BLN, low doping
III.
DEVICE ARCHITECTURE
Lateral NLDMOS and PLDMOS devices were designed
based on TCAD simulations. These devices were optimized to
maintain the required operating voltage with an appropriate
margin for ESD and minimal operating resistance (RDSON).
Each device was constructed with additional two-deep
implant layers, with the intention to share implants between
devices to maintain low wafer cost (Figure 7).
Figure 8 – Lateral NDMOS construction
Figure 7 – process flow of key steps (NLDMOS and PLDMOS
process steps are marked in green and red respectively)
A drift layer was placed in the drain area to connect the
isolated drain with the transistor gate. A resurf (reduced
surface field) layer was constructed underneath the drift layer
to balance the charges in the depletion region between the two
layers in order to maintain the required breakdown voltage.
Figure 9 – SEM cross section of Lateral NDMOS transistor
(corresponding to figure 8)
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IV.
CMOS PROXIMITY
The DTI process may introduce significant stress across the
wafer. This stress can be measured in a wafer bow test during
the process. DTI stress may also have an affect on devices
which are placed in close proximity to DTI pattern. In this
work, DTI proximity to transistors was investigated through
configuration of large and small DTI pockets.
The results of the study showed a parametric shift of
PMOS transistors in relation to DTI proximity. A 50mv Vt
shift was measured on PMOS transistors, (figure 10a) which
were placed in proximity to DTI but had no significant effect
for NMOS transistors (figure 10b). As the distance between
the transistor and DTI increased, the shift was reduced, but was
still noticeable compared to a reference transistor which was
placed outside of any DTI proximity. Having this dependence
can complicate the modeling of the PMOS transistors and is
not desired.
Figure 10b – Vt shift due to NMOS transistor proximity to DTI
comparing large and small DTI pocket configurations
It was found that this problem could be solved by adding
patterns of shallow trench isolation in proximity to the tested
transistors. This approach reduced the DTI dependence
significantly for transistors which were embedded in a large
pocket; however, this did not solve the parametric shift of
single transistors in small pockets. The single transistor case
can be addressed by keeping consistent layout and fixed DTI
distance.
V.
TCAD STRESS STUDY
Epi and DTI module processing appear to contribute
greatly to final stress distributions across the wafer. Figure 11
demonstrates the stress evolution with the annealing
temperature. Temperatures above 1050 C are required to
significantly minimize the stress localized in the vicinity of
DTI. Reduction of the residual stress is desirable for meeting
stringent reliability requirements such as gate oxide integrity.
Figure 11 - Silicon stress dependence on annealing temperature
Figure 10a – Vt shift due to PMOS transistor proximity to DTI
comparing large and small DTI pocket configurations
VI.
LDMOS DEVICE TARGETS
Figure 12 presents the device targets which were achieved
for 45V and 70V operations. Figure 13 shows how these
devices compare to the figure of merit of similar smart power
technologies.
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BVDS
(volt)
RDSON
(mΩ x mm2)
VII. CONCLUSIONS AND SUMMARY
NLDMOS
45V
55
49
70V
82-90*
95-100
45V
55
130
70V
90
230
This paper discussed the challenges of fabrication of smart
power ICs on deep sub-micron CMOS technology.
Manufacturability of smart power products relies on the
understanding of key device, defectivity and module
integration sensitivities. Results demonstrate a strategy for
defining manufacturable window for epi processing, BLN
doping, device proximity to DTI and defect reduction via stress
reduction and process optimization.
PLDMOS
Figure 12 – DMOS targets for BVDS and RDSON
ACKNOWLEDGMENT
* NLDMOS 70V device is currently released with 82V BVDS capability, but
with further architectural improvement BVDS of 90V can be achieved.
The authors would like to thank the ON Semiconductor
failure analysis team for providing the cross sections which are
described in the paper.
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B. Desoete, A. De Smet, and P. Moens “A Multiple Deep Trench
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Figure 13 – Figure of merit for smart power technologies with the
NLDMOS devices of Figure 12
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