Memory and Memory Compiler

Memory and
Memory Compiler
Chih-Tsun Huang (黃稚存)
Department of Computer Science
National Tsing Hua University
Common Memory Types
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SRAM
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DRAM
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Static Random-Access Memory
Dynamic Random-Access Memory
Non-Volatile Memory:
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ROM
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Read-Only Memory
Flash memory
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Memory in System Hierarchy
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Commodity memory
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External IC
Chip select, output enable
Embedded memory
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Internal module
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Common Memory Interface
cen
oen
address
q
data
write
SRAM
read
clk
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Dual-Port vs. 2-Read-1-Write
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Memory Array
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Artisan SRAM Compiler
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This is not a step-by-step documentation
Read the user guide for the details
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SRAM Compiler (Generator)
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Common SRAM compiler tool
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By Artisan
Free (not really)
Common SRAM types
 Single-port SRAM
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High-speed
High-density
Dual-port SRAM
Single-port, two-port register file
Thanks to the (free?) memory compiler, it is very
common to use a large amount of memory instances
in digital designs
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Several hundreds to a few thousands
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Location of Memory Compiler
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Artisan memory compiler comes with the library usually
 For UMC 0.18um process, it’s in
/theda21_2/CBDK018_UMC_Artisan/cur/CIC/Memory
TSMC 0.18um process:
/theda21_2/CBDK018_TSMC_Artisan/cur/CIC/Memory
 Three memory types are supported
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ra1sh: high-speed single-port SRAM
ra1sh: high-speed borderless bit-cell single-port SRAM
ra2sh: high-speed dual-port SRAM
Other naming convension:
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sd: high-density
rf: register files
rod: diffusion programmable ROM
The usage is similar to other Artisan cell library
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Documents and Executables
(UMC 0.18um)
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The user guides are in
 ra1sh_1/doc/user_guide/ra1sh.pdf
 ra1sh_2/doc/user_guide/ra1sh.pdf
 ra2sh/doc/user_guide/ra2sh.pdf
The executables (Java byte-code)
 ra1sh_1/bin/ra1sh
 ra1sh_2/bin/ra1sh
 ra2sh/bin/ra1sh
Invoke the binary by
/theda21_2/CBDK018_UMC_Artisan/cur/CIC/Memory/ra1sh_1/bin/ra1sh
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The usage is very clear if you refer to the documents
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Documents and Executables
(TSMC 0.18um)
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The user guides are in
 ra1shd/doc/user_guide/ra1shd.pdf
 ra2sh/doc/user_guide/ra2sh.pdf
 rf1sh/doc/user_guide/rf1sh.pdf
 rf2sh/doc/user_guide/rf2sh.pdf
 rodshd/doc/user_guide/rodsh.pdf
The executables (Java byte-code)
 ra1shd/bin/ra1shd
 ra2sh/bin/ra2sh
 rf1sh/bin/rf1sh
 rf2sh/bin/rf2sh
 rodshd/bin/rodshd
Invoke the binary by
/theda21_2/CBDK018_TSMC_Artisan/cur/CIC/Memory/ra1sh/bin/ra1shd
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The usage is very clear if you refer to the documents
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Interface
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Parameters
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Instance name: memory module name
Number of words: total addresses
Number of bits: bits of a word
Multiplexer width
Frequency
Ring width: power rings of the memory
Views (models/documents)
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Postscript Datasheet: *.ps
Verilog model: *.v
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Synopsys model: *.lib
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Memory simulation model
Synthesis models: fast, typical, slow
You should assign a user-specified library name for these model
PrimeTime model
LVS netlist
GDS II layout
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Note
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Every time you change the parameter, select Update button to
make it effective
Most of the parameters have valid range, you should check the
log window to see if the input value is invalid
Multiplexer width is used to change the aspect ratio (geometric
shape) of memory
 Usually a square is preferred
 You can preview it in relative footprint window
Postscript can be converted to PDF if you don’t have a postscript
viewer
 Online converter: http://ps2pdf.com/convert.htm
You can also save a specification file and load it afterward
 » Utilities » Write Spec
ra1sh –spec <spec_file>
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HS-SRAM-SP
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SRAM-SP
(TSMC 018)
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HS-SRAM-DP
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Datasheet
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Modern SRAM designs are synchronous
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The control is very simple
Can you control the single-port SRAM?
How about the dual-port SRAM?
How to perform the Verilog simulation?
How to perform the APR process?
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Synthesis Using Design
Compiler
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When generating synthesis model, there is a prompt to enter
library name
 USERLIB by default
 If the memory instance is called RAM1024x16
 There will be 3 plaintext synthesis library
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RAM1024x16_slow_syn.lib
RAM1024x16_typical_syn.lib
RAM1024x16_fast_syn.lib
You can convert them into binary DB format
In dc_shell
read_lib RAM1024x16_slow_syn.lib
write_lib USERLIB
lappend link_library "USERLIB.db"
lappend target_library "USERLIB.db"
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Single-Port SRAM Output-Enable
Timing
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Single-Port SRAM Read-Cycle Timing
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Practical Read-Cycle Timing
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Single-Port SRAM Write-Cycle Timing
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Practical Write-Cycle Timing
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Single-Port SRAM Timing Parameters
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Modern SRAM Controls
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Chip Enable (CEN)
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Output enable (OEN)
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Write Through
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Write Mask
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Sometime by multi-bit WEN
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Remarks – Embedded Memory
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Black boxes to the designer in both front-end and backend phases
Very Important to master the memories for a realistic
design
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The amount of embedded memories
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Many interfaces are similar to memory protocol
 BUS interface
 Memory-based IOs
Several hundreds to a few thousands
Area of memories dominates the system area
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