A Novel Self-Calibration Scheme for 12

A Novel Self-Calibration Scheme for 12-bit 50MS/s
SAR ADC
In-Seok Jung
Yong-Bin Kim
Department of Electrical
and Computer Engineering
Northeastern University
Boston, United States
[email protected]
Department of Electrical
and Computer Engineering
Northeastern University
Boston, United States
[email protected]
Abstract— This paper presents a low-power 12-bit 50MS/s successive approximation register (SAR) analog-to-digital converter
(ADC) using single input condition for Built-In Self Test (BIST)
that uses a novel self-calibration scheme to reduce both offset
voltage of a comparator and capacitor mismatch of the DAC.
The proposed self-calibration scheme changes the offset voltage
of the comparator continuously for every step to decide onebit code. The changed offset voltage of the comparator is able to
cancel not only inherent offset voltage of the comparator but also
the mismatch of DAC. Consequently, the total mismatch error
of both the comparator and capacitor of DAC can be reduced.
Compared to the converters that use the conventional procedure,
INL and DNL are reduced by about 47% and 52%, respectively.
The prototype was designed using 0.13μm single poly 6 metal
standard CMOS technology. The ADC achieves a SNDR of 65.6
dB and consumes 4.62 mW. The ADC core occupies an active
area of only 240μm×298μm Using 1.2V supply and the sampling
rate of 50 MS/s,.
margin and doubled input range. However, in order to generate
differential input from single-ended input, the balun is required
for suitable input frequency range and this component is not
only hard to be integrated but also has high cost. Therefore, it
makes more sense to use single-ended input ADC for on-chip
BIST hardware implementation. However, in general, it is not
easy to design the high resolution ADC using single-ended
input because of the inherent drawbacks of single-ended input
such as noise issues.
Among single-ended ADCs, pipe-line ADC type has been
used in the conventional BIST algorithm implementation.
However, successive approximation (SAR) analog-to-digital
converter(ADC) is being magniﬁed for mid-range sampling
speed(50∼100Mhz) recently [4] because SAR ADC is more
suitable than pipe-line ADC for BIST system due to its
lower power consumption and less area overhead comparing
to the inherited speciﬁcation of pipe-line ADC. Although SAR
ADCs are used in many different applications and has good
advantages such as low power and small die area compared
other ADCs using other architecture such as pipeline, there
are several drawbacks such as the mismatch of capacitor array
for charge-redistribution and offset voltage of comparator of
ADC.
In order to overcome those problems, a single-ended input
SAR ADC using a novel self-calibration method is proposed
in this paper. In more detail, this paper presents a SAR
ADC design in 130nm CMOS process that uses a chargeredistribution DAC to achieve a high resolution and low
power consumption. The proposed ADC exploits offset control
technique for the comparator to reduce the capacitor matching
issue of the metal-insulator-metal(MIM) capacitors in nanoscale CMOS technologies to obtain 12-bit resolution while
dissipating low power. The power consumption of the SAR
control logic circuit is further reduced by highly optimizing
the the control logic using asynchronous circuits. The offset
controller measures the comparator offset during each bit
conversion period and store the offset code into register one
time, and the effective input voltage of the comparator for each
conversion period is adjusted continuously with the offset code
stored in the register.
The remainder of this paper is organized as follows. Section
I. I NTRODUCTION
With technology scaling, the cost for test and measurement
is becoming a dominant factor for integrated circuits because
test cost remains the same even if the unit chip cost decreases
with the decrease of the minimum feature size. In particular,
test cost of communication components including RF circuits
is more expensive because they should test more speciﬁcations
such as linearity, IMD3, and S parameters. One of the solutions
for these problem is to employ Built-In-Self-Test(BIST). By
integrating BIST with the circuits, the increased yield and
reduced test cost can be accomplished [1].
The BIST methodology in [2] uses FFT , ADC, and control
circuit that connects the feedback loop between the output of
FFT and the monotonic capacitor array [2], [3]. The ADC
is used to convert the analog output of the Device-UnderTest(DUT) to digital signal, and then the converted digital
value as ADC output is observed through FFT. To get the
useful output value of the FFT, either FFT having high the
number of FFT point or High resolution ADC is needed.
The BIST methodology used in [2] is one-chip solution that
includes ADC in the chip to convert the output of DUT
directly, which means that the ADC should be single-ended
input.
It is well known that differential input in ADC has several
advantages compared to single-ended input such as high noise
978-1-4799-4132-2/14/$31.00 ©2014 IEEE
5
σ(Δβ)
Aβ
=√
β
W ·L
II introduces the mismatch factors of SAR ADC using chargeredistribution DAC, and Section III describes the proposed
SAR ADC using self calibration method. The simulated results
including post layout simulation are discussed in Section IV
to prove the proposed design, followed by the conclusion in
Section V.
where, ΔVt is the threshold voltage deferences, current
factor differences Δβ (β = μCox W/L [8]), W is the transistor
gate-width and L the transistor gate-length, and the proportionality constants AV t and Aβ are technology-dependent.
The effect of the mismatch become serious with scaling
process. The matching of the minimal size device degrades
with scaling. This is an important concern for the design of
circuits since the device mismatch starts affecting the noise
margin [9] and mismatch mitigation techniques cannot be
widely applied due to their large area overhead [7].
Obviously, according to equation (3), the transistor size
need to be increased by factor of 4 in order to reduce the
offset by 2 times. This calculation shows that the sizing is not
practical due to the excessive area and power consumption
cost. However offset calibration is necessary to efﬁciently
achieve good accuracy.
The basic idea for the calibration is to deliberately introduce
some imbalance to compensate for the offset. Such imbalance
can be either by capacitance loading [10] or current injection
[11], or even voltage difference [12]. To calibrate the offset
voltage, the differential inputs of the comparator are usually
tied together to a certain common mode voltage, which should
be the same as that when the comparator is in real operation,
and the comparator output is monitored and fed back to the
state machine to control the imbalance.
II. D EVICE MISMATCH ANAYSIS OF SAR ADC
Two main mismatch errors in SAR ADC are capacitor
mismatch error of the DAC and offset error of the comparator.
A. DAC mismatch
The conversion linearity of the SAR ADC is subject to
circuit components’ non-idealities. In case of charge redistribution SAR ADC, when matching is accurate, the SAR ADC
performs an ideal binary search to convert the sampled analog
input into an N-bit binary code. The mismatch of capacitor is
composed of global and local effects. The edge effect and the
oxide effect of the capacitor are other two variables in different
point of view. The relationship is given by the equation (1).
ΔC
= Kle C −3/2 + Kge C −1 + Klo C −1 + Kgo
(1)
C
Where the Kle is the local edge effect factor, Kge is the
global edge effect factor, Klo is the local oxide effect factor,
and Kgo is the global oxide effect [5].
When capacitor mismatch is present, the ADC transfer curve
is highly distorted, especially when small capacitors are used
for fast settling and to reduce power consumption. As a result,
the decision levels may no longer be uniformly distributed over
the full input range.
The relationship between capacitor mismatch error δ and the
resolution of N-bit charge redistribution SAR ADC is given
by equation (2) [6].
√
1 + δ + 1 + 2δ − 3δ 2
Nmax = log2 (
)
(2)
2δ
When the technology is deﬁnite, the capacitor mismatch
error δ is ﬁxed, and the maximum value of capacitor array N
can be calculated by equation (2).
III. P ROPOSED SELF - CALIBRATION METHODOLOGY
Figure 1 shows an example of 4-bit SAR ADC operation
to get digital output codes and their SAR architecture, where
the VDAC signal in Figure 1(a) is shown. In the case of time
period for second MSB decision and LSB decision, the errors
can be occurred by mismatch errors in this particular case.
In addition, the value of mismatch errors in the second time
period, e(a) and e(b) should be same.
The proposed self calibration method adjust the input
refereed offset voltage of the comparator in ﬁgure 1(b) for
each conversion period. In the ﬁrst step called M OD1, the
offset controller in Figure 2 measure the offset voltage of the
comparator, then adjust the 8 capacitor arrays of Figure 2. The
digital code to adjust offset voltage of the comparator is stored
in 8-bit register. For 12-bit SAR ADC, 12 registers with 8-bit
word-line are required. After all of the 12 codes are saved, the
offset controller changes the offset voltage of the comparator
continuously by using the stored code in the registers.
More details about getting the code to adjust the offset
voltage of the comparator are as follows. Firstly, the Vin is
set up to Vref /2 as reference voltage, i.e., 0.6V. At the same
time, DAC sets up its output voltage at the Vref /2 using
the capacitor array and charge redistribution algorithm, This
voltage is not going to be exactly Vref /2 because there is a
mismatch error. Therefore, reference voltage is different from
DAC output voltage as much as mismatch error. The comparator offset controller ﬁnds the error code for the capacitor arrays
B. Offset mismatch
An ADC offset is a random additive error typically resulting
from the comparator offset. In a single-channel ADC, the
offset error creates a DC tone and the comparator is usually designed to have input-referred noise less than 1 LSB.
With low power supply voltage, 1 LSB should be less than
V ref /2N bit. For example, 1 LSB is 244.14 μV in the 12-bit
SAR ADC using 1V Vref .
The input referred offset of the comparator used in the ADC
will possibly degrade the overall ADC performance, so it is
better to be minimized. Such offset is primarily function of
threshold mismatch, current factor mismatch, and transistor
dimension as below [7]
AV t
σ(ΔVt ) = √
W ·L
(4)
(3)
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Sampling
Can be a error
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VIN
Input referred offset error
Sampled
input
2NC
2C
C
C
e(a)
Vref/2
Mismatch error of DAC
SAR
Logic
Offset
Controller
VREF
8bit Register
X12
Cap-DAC
DAC
Driver
e(b)
Time (t)
Fig. 2.
The proposed SAR ADC structure
(a) A example of 4-bit SAR ADC operation
VIN
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Fig. 1.
A example of 4-bit SAR ADC operation (a) and SAR ADC
architecture (b)
Fig. 3.
that minimize the mismatch error by changing the number of
connected capacitor arrays.
To avoid a high-frequency clock generator and a pulse
width modulator (PWM) for SAR logic, the proposed ADC
uses an asynchronous control circuit to internally generate
the necessary clock signals and to reduce switching power
consumption. The generated clock signal is used for the
comparator and SAR logic. However, for M OD1 operation,
the SAR ADC uses input sampling clock frequency because
M OD1 process does not have to be run fast. In the proposed
design, the sampling frequency is 50MHz and the comparator
is operated by the same clock during M OD1 operation. For
normal operation, the SAR logic does not support the offset
controller and it bypasses the output of the comparator to DAC
driver. However, SAR needs to support both offset controller
and DAC during M OD1. The eight capacitor arrays connected
to the comparator are used to adjust the effective input voltage
of the comparator by compensating the offset voltage.
The offset controller and 8-bit registers are synthesized
using digital standard cell library supported by the process
foundry company.
The layout of the proposed ADC
0.058 mm2 . The switches for capacitors are placed close to the
capacitor arrays to reduce any parasitic components. The logic
control circuit has been optimized for power consumption and
area using asynchronous logic, and the layout of the digital
logic circuit is more compact. The input signal capacitance
for sample and Hold Ampliﬁer (S/H) and total capacitance of
capacitive DAC are 1.05 pF and 20.24 pF, respectively. The
size of the synthesized offset controller including registers is
0.0081 mm2 , and the area overhead of the proposed method
is 12 %.
The summarized overall performance of the proposed ADC
is shown in Table I. The proposed ADC achieves an ENOB of
11.04 bit and SNDR of 65.6 dB for 25 MHz input frequency.
At 50 MS/s, the average power consumption including the
output buffers and the offset controller is 4.62 mW. Compared
to the ADC operation without the offset controller, the power
increased consumption is 23%. However, the power consumption of the offset controller will be decreased further with
process scaling.
The simulated static performance for differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed
ADC are shown in ﬁgure 4. The peak DNL values are between
-0.82 to 0.75 LSB and the peak INL values are -1.42 to 1.05
LSB. Figure 5 shows the dynamic performance of the proposed
ADC with the data of simulated SNDR and SFDR vs. input
frequency of 50MS/s. When the input frequency is 1 MHz,
IV. S IMULATION RESULT
The proposed work is designed in a 130nm standard CMOS
process for fabrication. Figure 3 shows the layout and ﬂoorplan of the core part. The occupied total area including powerring of the ADC is 0.072 mm2 , with the ADC core taking only
7
the ADC has peak SNDR and SFDR of 65.6 dB and 75.1 dB,
respectively.
TABLE I
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P ERFORMANCE SUMMARY OF THE PROPOSED SAR ADC
V. C ONCLUSION
Speciﬁcations
This work
Process
Resolution
Total area
Active area
Supply
Input range
Sampling rate
DNL / INL (LSB)
ENOB
SNDR
SFDR
Power
130 nm
12 b
0.0715 mm2
0.0582 mm2
1.2 V
0.4 - 1.2 V
50 MS/s
-0.82∼0.75 / -1.42∼1.05
11.04 @ Fin = 25 MHz
65.6 dB
75.1 dB
4.62 mW
A 12-bit 50 MS/s SAR ADC using a novel self-calibration
method has been presented in this paper. The proposed method
and the proposed offset controller to compensate the offset
voltage of the dynamic comparator have also been presented.
The proposed method diminishes both mismatch error of the
DAC and offset error of the comparator, thus the linearity
of the ADC can be increased by 52% with 23% overhead
compared to the conventional ADC. Consequently, ENOB
is increased by 1.6 in spite of the use of single endedinput SAR ADC. The prototype ADC using 130nm standard
CMOS process shows the SNDR of 65.6dB for 25 MHz input
frequency and consumes 4.62 mW with output buffer. The
proposed ADC will be a good reference to overcome the
presumed limit of the resolution of SAR based ADC using
single-ended input.
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Fig. 4.
Simulated INL and DNL at 64MS/s
Fig. 5. Simulated SNDR and SFDR performance versus input frequency at
64MS/s
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