Successive Approximation ADC

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LTE, TUM, SS 2012
Successive Approximation ADC
Specifications In this LAB, a binary search SA ADC will be built, fulfilling the function of
sampling a slow signal coming from a sensor. The specifications are given as follows:
Input voltage range
Input frequency range
Supply voltage (Vdd )
Ground voltage (Vgnd )
Reference voltage
Required SNR
−− (TBD)
0-20kHz
2V
0V
2V
> 45dB (8bits)
System architecture of an typical SA ADC is shown in Fig.2:
Figure 2: System architecture of a SA ADC
Problems for system design
1. Concept and Theories
(a) What is the basic working principle of a binary search based SA ADC?
(b) How many cycles does the SA ADC need for one conversion?
(c) Compare Binary weighted and Unit element SA ADC.
(d) Describe the advantages of Segmented DAC over Unit element and Binary weighted
DAC.
(e) What are the advantages of using charge distribution DAC in SA ADC?
(f) Which circuit elements in SA ADC causes DNL and INL errors? State the equation
describing relation between INL and DNL errors.
Mixed-Signal IC Design LAB
11
(g) What is the maximum achievable theoretical SQNR for a N bit ADC? Why is ENOB
always less than designed resolution of an ADC?
(h) Consider a 3 bit ADC with ideal 1LSB = 0.2V i.e. Vref = 1.6V. The Fig.3 illustrates
the input-output transfer curve for an ideal and fabricated ADC.
Figure 3: Input-output transfer curve for a 3 bit ADC
i.
ii.
iii.
iv.
v.
Calculate the offset and fullscale error for the fabricated ADC.
Calculate the actual 1LSB for the fabricated ADC.
Calculate the new full scale voltage and the gain of fabricated ADC.
Calculate the DNL and INL errors for each step of input volatge.
Can DNL be less than -1LSB for ADC? Give reason.
(i) How are INL and DNL errors measured for a designed ADC?
2. Spectrum analysis
(a) DFT has to be used to analyze the frequency spectrum of the output bit stream.
Matlab provides a FFT function instead of DFT. What is the relationship between
these two?
(b) What are the relationships between the number of samples N, sampling frequency
fs , total sample time T and frequency resolution ∆f in a frequency spectrum?
(c) What is frequency leakage effect? How to avoid it?
(d) If the input frequency is unknow, window function (filter) has to be used to eliminate
frequency leakage effect. Please explain how the window functions works to suppress
frequency leakage.
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LTE, TUM, SS 2012
(e) Explain the way to calculate SNR from a frequency spectrum resulted from DFT
with window function.
(Please finish above problems before 8th, November 2012.)
3. Specification related
(a) Determine the reference voltage and the input voltage range.
(b) Determine the required number of cycles corresponding to one conversion and sampling frequency fs according to the given specification.
(c) Implement the SAR ADC behavior model by using Matlab/Simulink.
(d) If a constant DC input is given, draw a F (n) vs. time plot by Matlab simulations.
What characteristic is shown in such a plot?
(e) Add offset error to the comparator block, observe the conversion and draw F (n) vs.
time plot again. What happens this time?
(f) Plot the output spectrum for a periodical sinusoidal input voltage. How much is
the noise floor below the input signal? Compare the simulated SNR to your SNR
calculations.
(g) How can the effects of charge injection and clock feed-through from the switches and
offset of the comparator be minimized?
(h) Draw a state flow graph for implementing the control logic (SAR) block for the SA
ADC using segmented DAC.
(i) Implement the code required for Control logic (SAR) using Verilog.
(Please finish above problems before 13th, December 2012.)
Problems for circuit design
1. Macro-circuit level
(a) With the sampling frequency fs calculated above, determine the minimum operation
speed/bandwidth of the circuit.
(b) In switched capacitor (SC) circuits, what are the key elements affecting the operating
speed, why?
(c) In SC ADC, KT /C noise has to be considered. Calculate the minimum required
sampling capacitor Cs in this design if the rms noise should be smaller than Vlsb/2.
(d) What causes offset in Comparator circuits? Determine the comparator configuration
to overcome this offset error.
Mixed-Signal IC Design LAB
σINL
σDNL
No. of switches
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Binary Weighted
B
2( 2 )−1 σε
2σINL
B
Unit Element
B
2( 2 )−1 σε
σε
B
2 −1
Tabelle 1: Binary Weighted Vs Unit Element DAC
(e) Table 1 gives standard deviation of INL and DNL errors and number of switch
elements for binary weighted and Unit element DAC,
where σε = standard deviation of circuit components and B = No. of bits in ADC
Assuming σε = 0.1% find a trade off between DNL and number of switches for 8 bit
SA ADC using segmented DAC.
(f) Design the schematic for SAR ADC with segmented DAC in Cadence Analog Mixed
Signal environment using ideal switches and circuit blocks. Verify the functionality
of the circuit.
2. Transistor level
(a) Modify the schematic by replacing all components except comparator with transistors.
(b) How to select the transistor type in switches (TG/NMOS/PMOS)? Give your reasons.
(c) Give a slow ramp input and check whether there are missing codes at the output.
By using a golden DAC, the output code can be translated into a voltage Vout close
to Vin , plot Vout − Vin vs. time.
(d) Repeat the above step with offset in comparator.
(e) Give a sinusoidal input and plot Vout − Vin vs. time again. Compare the value to
VLSB and see whether they are always within ±VLSB /2.
(f) Give a sinusoidal input (2KHz with maximum possible input voltage) and plot the
output spectrum. Evaluate the SNR and compare the output with matlab results.
Reference books
• D.A. Johns; K. Martin, Analog Integrated Circuit Design, Wiley, 1997
• B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
• R.J. Baker; H.W. Li; D.E. Boyce, CMOS, Circuit Design, Layout and Simulation, Wiley,
1997
• R. Gregorian; G.C. Temes, Analog MOS Integrated Circuits For Signal Processing, Wiley,
1986
• S.J. Orfanidis, Introduction to Signal Processing, Prentice Hall, 1998

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