Solutions to review problems for Exam I INEL 4207

Solutions to review problems for Exam I
INEL 4207 - Digital Electronics - Spring 2014
1. For the following circuit, specify the required values of VDD , RD and W/L such that high and low
output voltages equal to VOH = 2V and VOL = 0.1V , respectively, are obtained, and so that the
current drain from the supply in the low-output state is 20µA. The transistor has Vt = 0.5V and
µn Cox = 100µA/V 2 .
VDD
RD
vout
vin
Q
ANSWER:
VDD = VOH = 2.0V
iD =
VDD − VOL
2.0V − 0.1V
→ RD =
= 95kΩ
RD
20µA
1
2
(µn Cox )(W/L)(2(vGS − Vt )vDS − vDS
2
W
20µA
≃ 1.38/1
= 1
2 ) (2(2V − 0.5V )(0.1V ) − (0.1V )2 )
L
(100µA/V
2
iD = 20µA =
2. The pull-down (PD) network for a complex CMOS gate is shown below. Determine (i) the logic
function, (ii) the graph diagram that correspond to the PD network, (iii) the graph diagram that
correspond to the pull-up network needed to implement the logic function, and (iv) the (W/L) ratios for
all NMOS and PMOS transistors if the circuit is based on a the reference inverter with (W/L)n = 2/1
and (W/L)p = 5/1.
1
Y
A
A
G
D
1
B
D
E
G
B
E
H
C
H
F
C
black: PDN
red: PUN
F
0
ANSWER:
i Y¯ = A(B(C + HF ) + G(F + CH)) + DE(F + CH + GBC)
ii See the figure above.
0
iii For the PDN, the longest path involves 5 transistors; D − E − G − B − C. So
W/L)B,C,D,E,G = 10/1
Transistors A, F and H are on path A − B − H − F , so
(W/L)A,F,H = 15/2
For the PUN, the longest path are A − G − H − F , C − H − G − D and C − H − G − E. These
paths have four transistors, so
(W, L)A,C,D,E,F,G,H = 20/1
The remaining transistor B will be in paths B − H − F , B − G − D and B − G − E, so
(W/L)B = 10/1
3. Consider a matched CMOS inverter fabricated in the 0.13-µm process for which Vtn = −Vtp = 0.5V ,
VDD = 1.8V , µp Cox = µn Cox = 300µA/V 2 . If the load capacitance C = 20f F , use the method of
average currents to determine the required (W/L) ratios so that tp ≤ 20ps.
ANSWER: W/L = 3.75
4. For the saturated-load inverter shown below,
VDD
Q2
vOUT
Q1
vIN
VOH = VDD − Vt2
where Vt2 is given by
)
√ (√
√
Vt2 = 0.5V + (0.3 V )
VOH + 0.8V − 0.8V
(a) If VDD = 1.8V , use an iterative process to determine Vt2 and VOH .
ANSWER: Vt2 = 0.5V , VOH = 1.3V → Vt2 = 0.67V , VOH = 1.13V → Vt2 = 0.65V , VOH =
1.15V → Vt2 = 0.65V . Thus, VOH = 1.15V
(b) Find the ratio of (W/L)2 to (W/L)1 needed to get VOL = 21 Vt0 when vIN = VOH .
ANSWER: Q1 operates in triode mode since VDS,1 = VOL = 12 × 0.5V = 0.25V < vGS,1 − Vt1 =
1.15V − 0.5V = 0.65V . Thus,
( )
(
)
µn COX W
iD1 =
2(0.65V )0.25V − (0.25V )2
2
L 1
For Q2 , vGS,2 = 1.8V − 0.25V = 1.55V and
iD2 =
µn COX
2
(
W
L
)
2
(1.55V − 0.5V )
2
Setting iD1 = iD2 and rearranging,
)
(
W⧸
2
L 1
(1.05V )
) =
(
= 4.2
2(0.65V )0.25V − (0.25V )2
W⧸
L 2
(c) The gate of Q2 is removed from VDD and connected instead to a new supply VDD2 . Find the
voltageVDD2 that will make VOH = 1.8V .
ANSWER:
)
√ (√
√
1.8V + 0.8V − 0.8V = 0.72V
Vt2 = 0.5V + (0.3 V )
VDD2 = VOH + Vt2 = 1.8V + 0.72V = 2.52V
5. The pull-down (PD) network for a complex CMOS gate is shown below. Determine (i) the logic
function, (ii) the graph diagram that correspond to the PD network, (iii) the graph diagram that
correspond to the pull-up network needed to implement the logic function, and (iv) the (W/L) ratios for
all NMOS and PMOS transistors if the circuit is based on a the reference inverter with (W/L)n = 2/1
and (W/L)p = 5/1.
Y
Y
F
F
A
D
D
A
G
G
C
C
B
E
E
B
1
black: PDN
A
D
F
red: PUN
1
C
0
G
E
B
0
i Y¯ = A(B + CEG) + F (BC + EG) + D(E + BCG)
ii See the above figure.
(
)
iii For the PDN, W⧸L
= 4 × 2⧸1 = 8⧸1 , (W/L)F 2 × 2⧸1 = 4⧸1 .
A,B,C,D,E,G
For the PUN, four devices are(involved
) on the paths through transistors A−C−G−D, B−C−F −D
W
and A − F − G − E. Thus,
⧸L
= 4 × 5⧸1 = 20⧸1 .
A,B,C,D,E,F,G
6. Use the method of average currents to find the propagation delay for a minimum-size CMOS inverter
for which µn COX = 3µp COX = 180µA/V 2 and (W/L)n = (W/L)p = 0.75µm/0.5µm, VDD = 3.3V
and the load capacitance is 2f F/µm× transistor width plus 1f F per device (i.e. transistor). Use
Vtn = −Vtp = 0.7V .
Note: This answer use the formulas from the textbook. You should do the problem finding the currents
directly, using the mosfet’s formulas and not using the textbook’s formulas.
Note 2: The problem statement should read: “the load capacitance is 2f F/µm× transistor width
(expressed in µm) plus 1f F per device (i.e. transistor)”, so CL = 2(1f F × 0.75 + 1f F ).
ANSWER:
αn
2
=
7
4
=
tP HL
=
αp
=
tP LH
=
tp
=
−
3Vtn
VDD
−
3(0.7V )
3.3V
(
+
Vtn
VDD
2
7
4
kn′
α C
( W n)
L
n
+
VDD
2
)2
( 0.7V )2 =
3.3V
=
2
≃ 1.73
1.16
1.73 × 2 × (1f F + 2f F × 0.75)
= 9.7ps
(180µA/V 2 )( 23 )(3.3V )
( 0.7V )2 = αn = 1.73
+ 3.3V
1.73(5f F )
= 3tP HL = 29.1ps
(60µA/V 2 )( 32 )(3.3V )
29.1ps + 9.7ps
= 19.4ps
2
7
4
−
3(0.7V )
3.3V
7. Using the reference inverter shown in the following diagram,
(a) draw the schematic for a CMOS gate that implements the following logic function of inputs A,
B, C, D and E.
A(B + C(D + E))
(b) for your design, indicate the
W
L
ratio for each transistor that would minimize the total area.
VDD=5V
B
A
VDD=5V
vIN
3/1
4.5/1
C
(W/L)P=3/1
9/1
9/1
D
9/1
E
vOUT
A
(W/L)N=1.5/1
B
4.5/1
2.25/1
D
8. (30 points) For the following dynamic-logic gate,
4.5/1
4.5/1
4.5/1
C
E
VDD
φ
CL
A
B
φ
assume that the body effect can be neglected, CL = 0.1pF , VDD = 5V , and that, for the three nmos
transistors, µn Cox = 0.3mA/V 2 , (W/L)n = 1/1, and Vtn = 1V . Use the average current method and
an equivalent transistor to estimate the fall time, tf , during which the voltage at CL will drop from
90% to 10% of VDD during the evaluation phase, when A and B both equal to logic-1 (5V ).
ANSWER:
Replace the three nmos transistors with a single transistor, Meq , with length equal to 3L, where L is
the length of the original nmos transistors. The equivalent transistor’s (W/L)eq = 1/3.
When VCL = 0.9 × 5V = 4.5V = VDS,Meq > VGS,Meq − Vtn = 5V − 1V = 4V ,
iCL (4.5V ) =
300µA/V 2 1
2
(5V − 1V ) = 0.8mA
2
3
When VCL = 0.1 × 5V = 0.5V = VDS,Meq < VGS,Meq − Vtn = 5V − 1V = 4V ,
iCL (4.5V ) =
tf ≃ 0.1pF
)
300µA/V 2 1 (
2(5V − 1V )0.5V − (0.5V )2 = 0.1875mA
2
3
4.5V − 0.5V
4V
≃ 0.1pF
= 0.8ns
0.5mA
+ 0.1875mA)
1
2 (0.8mA
9. The transmission gate shown below is fabricated in a CMOS techology for which µn Cox = 4µp Cox =
1
0.3mA/V 2 , |Vt0 | = 0.5V , γ = 0.3V 2 , 2ϕf = 0.85V , and VDD = 1.8V . Let Qn and Qp have (W/L)n =
(W/L)p = 1.5, and have their respective substrates connected to 0V and VDD , as usual. The total
capacitance at the output node is 15f F .
VDD
Qn
vi
vO
Qp
C
Using the average current method, estimate
(a) (15 points) tP LH , defined as the time it takes vO to transition from 0V to vDD /2, when an input
vi = VDD is applied, and
ANSWER:
• For vO = 0V ,
vDS,N
=
vSD,P = 1.8V = vGS,N = vSG,P
Both QN and QP are saturated and
iN
iP
i1
(0.15mA)(1.5)(1.8V − 0.5V )2 = 380µA
(0.15mA)(1.5)
(1.8V − 0.5V )2 = 95µA
=
4
= iN + iP = 475µA
=
• For vO = VDD /2 = 0.9V , vDS,N = vSD,P = 0.9V = vGS,N , and vSG,P −|Vtp | = 1.8V −0.5V =
1.3V , so QN is saturated and QP is operating in triode mode.
(√
)
√
1
VtN = 0.5V + (0.3V 2 )
0.9V + 0.85V − 0.85V
iN
vSD,P
iP
i2
= 0.62V ⇒ vSG − VtN = 0.9V − 0.62V = 0.28V
= (0.15mA)(1.5)(0.28V )2 = 17.6µA
= 0.9V < vSG,P − |VtP | = 1.8V − 0.5V = 1.3V (triode)
(0.15mA)(1.5)
=
(2(1.3V )0.9V − (0.9V )2 ) = 86µA
4
= iN + iP = 103.7µA
• Now find the average current and the propagation time:
475µA + 103.7µA
= 289.35µA
2
= (15f F )(0.9V )/(289.35µA) = 46.7ps
iAV E
=
tP LH
(b) (15 points) tP HL , defined as the time it takes vO to transition from VDD to vDD /2, when an input
vi = 0V is applied.
ANSWER:
• For vo = 1.8V ,
vDS,N
=
vSD,P = 1.8V = vGS,N = vSG,P
Both QN and QP are saturated and
iN
iP
i1
(0.15mA)(1.5)(1.8V − 0.5V )2 = 380µA
(0.15mA)(1.5)
(1.8V − 0.5V )2 = 95µA
=
4
= iN + iP = 475µA
=
• For vo = 0.9V ,
vDS,N
vGS,N
= vSD,P = 0.9V
= 1.8V
vSG,P
=
0.9V
so QN is operating in triode mode and QP is saturated.
)
(√
√
0.9 + 0.85 − 0.85 = −0.62V
Vtp = −0.5 − 0.3
iP
iN
i2
(0.15mA)(1.5)
(1.8V − 0.9 − 0.62V )2 = 4.4µA
4
= (0.15mA)(1.5)(2(1.8 − 0.5)0.9 − 0.92 ) = 344.25µA
= 348.65µA
=
• Now find the average current and the propagation time:
iAV E
tP HL
475µA + 348.65µA
= 412µA
2
= (15f F )(0.9V )/(412µA) = 33ps
=

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