E3 239 Advanced VLSI Circuits High-Performance SRAM Design Rahul Rao IBM Systems and Technology Group Topics Introduction to memory SRAM basics and bitcell array (refresher) Current Challenges Alternative Cell Types (6 to 10T), Asymmetric Cells, Sub- threshold Cells, Low – leakage cells Impact of Variation, Assist Circuits BTI and impact on SRAMs Power Slide 1 The Balancing Act AL PL PR NL NR AR Large N: Better READ performance. If too large, trip voltage of inverter becomes so low that cell becomes unstable. Large A: Better Performance. If too large, storage node voltage goes high during READ, causing cell flip Large P: Increase stability. If too large, hard to WRITE 6-T Single Ended Read R/WWL WWL PL AL Qb PR AR NL WBL • Split word line for Read and Write • Single-ended Read / Differential Write • Full swing domino Read with short bit line Q NR R/WBL READ : R/WWL = VDD and WWL = GND WRITE: R/WWL = VDD and WWL = VDD Asymmetric 6-T Cells AL PR NR Sym R/WWL NL WWL PL PR AL AR Qb NL NR Asym Size AL NL AR PR NR PL AR Straight Active region Q Asym Vt WBL PL AL NL PR NR PL AR Higher Vt doping R/WBL Asym Device AL NL PR NR PL S-D are distinct AR (J. Kim, CICC 2010, J. Kim EDL 2011) Asymmetrical 6T SRAM: Device Sizing Read word-line separated from Write word-line Single-ended Read, differential Write R/WWL WWL 1.0 PL AL Weaker NMOS Qb PR 0 AR Q NR NL Shift of Q vs Qb curve 0.8 Sym.6T 0.6 Asym.6T with minimum size NL 160 mV 200 mV Iread 0.4 0.2 WBL Make the two sides unbalanced Trip voltage of PL-NL pair goes up 320 mV 340 mV R/WBL 0.0 0.0 0.2 0.4 0.6 Q (V) (J. Kim, ESSCIRC, 2006) 0.8 1.0 6T Asym SRAM in Double Gate Technologies Bias back-gate of NL to GND. Front-gate as cell device & sizing down NL Left and Right SNM become comparable Optimal SNM of asymmetrical cell 1.0 R/WWL WWL 300 mV 0.8 PL AL Qb sym. 6T PR Q 270 mV 0.6 Cell 3 w/ NL=0.25um 160 mV AR Cell 3 w/ NL=0.1um NR 0.4 NL (FG) 0.2 WBL 320 mV R/WBL 0.0 0.0 (J. J. Kim et al., ESSCIRC, 2006) 300 mV 0.2 0.4 0.6 Q (V) 0.8 1.0 Workhorse 6T-Cell WRITE READ WL=VDD WL=VDD 1 -> 0 HOLD 0->1 1 WL=0 0 0 1 Iread BL=GND BLb=VDD Pull Up Xr Access Xr: On Data driven on bit - lines Data Flipped by overcoming pull-up / pull – down Xrs BL=VDD BLb=VDD Pull down Xr Acess Xr: On BL, Blb pre-conditioned, and then floated, one line discharges thru the cell (Iread), voltage sensed, Data Retained BL=VDD BLb=VDD Access Xr Access Xr : Off Data Retained, due to back-to-back inverters Asymmetric MOSFET G S N+ P+ halo Tilted implantation for asymmetric S/D extension D Gate N+ P+ halo Sym. MOSFETP- Single Sided Halo S G SOI Modified Halo D S N+ N+ N+ P++ halo P- G D N+ P++ halo P halo Modified Implant Energy G D S N+ P+ halo P- Asymmetric MOSFET can be realized in multiple ways Net Effect: I (drain – source ) = I (source – drain) N+ P+ halo P- Asymmetric Access Transistors WL = VDD D S S VL=VDD BL= VDD WL = VDD D VR=0 Inner Cell D S S VL=0 BLb= VDD Read Operation • Access Transistor in Fwd Mode • Weaker than in Sym. Case • Read Disturb Noise Reduced BL= VDD D VR=VDD Inner Cell BLb= 0 Write Operation • L and R Access Transistor in Fwd and Rev Mode respectively Decoupled Read – Write Bitlines RWL WWL READ Path WBL WBLb RBL (L. Chang et al, VLSI Symp 05) Decoupled Read – Write Bitlines (L. Chang et al, VLSI Symp 05) Half-Select Disturb • During a Read or Write operation, half-selected cells on the selected wordline are actually experiencing “Read” operation – Disturb similar to Read-disturb BL ‘1’ WL0 WL1 BR BL ‘1’ ‘1’ BR ‘0’ ‘0’ Selected for WRITE ‘1’ COL0 Disturb failure can occur COL1 Half-Select in 8T • Array architecture approach – No column select. Floorplan such that all bits in a word are spatial adjacent • Gated Write wordline signal (Byte Write) – Local Write wordline “on” only for the selected block • Write-back scheme – RWL activated even during Write, all cell data in selected WL read out to D-latches – Dataout is then written back to half-selected cells Delayed Read-Modify-Write Delayed WRITE WWL=VDD 8T cell column 8T cell column RBL RBL W1 0(1) WBLb 1(0) WBL 0(1) WBLb WBL RBL Write Back Din_b Din Half-selected (WB) R1 Write Back Din_b WBL R pch R pch WR/ WB Din Selected (WR) Allow the column-select in 8T cell array by replacing “WRITE” with “READ-MODIFY-WRITE” One cycle delayed WRITE: Relaxed timing, No bandwidth loss Conditionally decoupling regeneration VDD: Read WWL RWL 0 VDD BL PL PR VR AR 0 AL VL VDD NR N7 BLb /WL 0: Read NL (K. Takeda et al, ISSCC 05) 10-T SRAM (word line) (write word line) WL and W_WL are boosted by 100mV (at 300mV VDD) - Successful write is ensured at the worst case corner ● ● Written values need to be inverted (J. Kim, et al, ISSCC 2008) Bit Interleaving WL (0.4V) W_WL (0V) BLB (0.3V) AL2 AL1 QB Q NL BL (0.3V) AR1 AR2 NR VGND (0.3V) WL (0V) W_WL (0.4V) BLB (0.3V) AL2 AL1 Q (0) QB (1) NL BL (0V) AR1 AR2 NR VGND (0.3V) Sub-threshold 8-T SRAM (B. Zhai, JSSC 08) Low leakage SRAM (S. Hanson , VLSI Symp ’08)
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