MOSFET and jFET and FET circuits

Analytical exercises, Circuits, Devices, Networks and Microelectronics
CDNuE
FETs and FET circuits
Version 3.19
Physical constants: OX = .0345fF/m
10-4. Suppose that for each of the transistors of
problem 10-1 its construct extends out on each
side by 1.0 m so that it occupies a rectangular
footprint of dimension W x (L + 2m). How large
of a circuit (number of transistors) can be
inscribed on the cross-section of a human hair of
diameter 40m for each case? Do not include
fractions of transistor footprint in your assessment.
10-1. Determine intrinsic conduction coefficient
K’ (in A/V2), conduction coefficient K, (in
A/V2), and conduction coefficients , (in A/V2)
for each of the following nMOS FETs.
(a) tOX = 34.5nm,  = 600 cm2/Vs, W/L
= 10m/1.0m
(b) tOX = 17.25 nm,  = 400 cm2/Vs, W/L
= 3.0m/0.6m
(c) tOX = 6.9 nm,  = 250 cm2/Vs, W/L
= 1.5m/0.25m
Hint: Area of ellipse =  4  ab
Answers: (a) 29 (c) 338
10-5. An nMOS Field-effect transistor has VTN =
0.6V , oxide thickness tOX = 12.5nm and intrinsic
conduction coefficient K’ = 125A/V2.
Determine:
Note: Units conversion essential unless you know
the quick trick.
Answers: (a) 60A/V2, 300A/V2, 600A/V2
(b) 80A/V2, 200A/V2, 400A/V2
(a) Conduction coefficient KN if W/L
= 2.0m/0.5m.
(b) the level of current for the active mode if
VGS = 2.2 V for (a) and the high-fields reduce
current level by a factor of 5.
(c) The minimum value of VDS (= VDSAT) for
operation in the active mode for (b)
(d) The value of V = VDS(min) (= VDSAT) if I
= 160A for operation in the active mode.
10-2. For the T77X wafer test data located at
http://www.mosis.com/requests/test-data
under the ON semiconductor 0.50 micron (C5)
process and a pMOS FET determine:
(a) COX
(b) Intrinsic conduction coefficient K’ for
the process.
(c) Conduction coefficient KP for a transistor
that has W/L = 5m/1.0m.
(d) Gate capacitance (Cgate) for the transistor
of part (c).
Answers: 250A/V2, 128A, 0.72V, 0.8 V
10-6. An nMOSFET has VTN = 0.5V , oxide
thickness tOX = 12.5nm and intrinsic conduction
coefficient 0COX = K’ = 125A/V2. Determine:
10-3. For the T67R_MM_NON_EPI wafer test
data located at
http://www.mosis.com/requests/test-data under the
TSMC 0.25 micron process nMOS transistor
determine:
(a) Capacitance/area in fF/m2
(b) mobility 0 in cm2/Vs
(c) Width Wn necessary for KN = 300A/V2
for a 0.6m technology (i.e. Ln = 0.6m).
(d) Gate capacitance for (c), in fF.
(a) Conduction coefficient KN for a
transistor that has W/L = 2m/0.5m.
(b) Gate capacitance (Cgate) for the
transistor of part (a).
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-10. The pMOS transistor for the circuit of
figure P5.6 has VTH = -0.8V and a 0COX =
40A/V2. It is fabricated under an L = 0.5 m
technology. Find the value of R and W necessary
to establish a drain current of 200 A and a
voltage at VD = 7.2V.
10-7. An nMOSFET for which VTH = 0.8V and KN
= 80A/V2 is in the active mode of operation.
(a) If the drain current ID = 180A, what is
VGS and what is the minimum VDS (= V) needed
for the transistor to be in the active mode?
(b) If the drain current ID = 720A, what is
the VGS and what is the minimum VDS (= V) for
the transistor to be in the active mode?
Answers: 2.3V, 1.5V, 3.8V, 3.0V
10-8. In the saturation (active) mode the drain
conductance gDS is a slope proportional to the
current level. Therefore gDS = I, for which  is
a MOSFET parameter. The parameter  also may
be expressed as 1/VA, where VA is defined as the
Early voltage (c.f. James Early, 1922-2004). For
the output trace represented by figure pF-5
determine:
Answers: 36k, 0.8m
10-11. The nMOS transistors for the circuit
shown have VTH = 0.8V and 0COX = 40 A/V2.
If they are fabricated under an L = 1.2m
technology, find values of R and of gate widths W1
and W2 necessary to yield voltages and currents
indicated.
(a) gDS and rDS (= r0)
(b) The value of VA for this technology
10-9. An nMOS transistor for which 0COX =
50A/V2 and VTH = 0.8V is used in a circuit for
which VGS = VDS = 3.3V. If the transistor is
fabricated under a 1.2m technology, what width
W is required for a current of 500A? Assume
current reduction factor 5 due to high fields.
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-12. Determine VG, ID, VS, VGS and VDS for the
following bias network. (assume resistances in k
unless indicated otherwise.)
10-14. Determine the operating point for the
nMOS 4-R bias frame (shown) for each of the
following values of the conduction coefficient K.
(a)
(b)
(c)
(d)
K = 1.0mA/V2
K = 5.0mA/V2
K = 20mA/V2
K = 100mA/V2
Answers: 2.0V, 0.134mA, 0.268V, 1.73V, 6.39V
10-13. Find
(a) operating point {VGS, ID, VDS} and VS.
(b) gm and gDS
Answers:
(a) {1.09V, 0.352mA, 5.07V}
(b) {0.79V, 0.427mA, 4.02V}
(c) {0.65V, 0.462mA, 3.53V}
(d) {0.57V, 0.483mA, 3.24V}
10-15. What is the transconductance gm for each
of the above cases of operating point?
10-16. If 0COX = 40 A/V2 is the intrinsic
conduction coefficient K’ for each of the above
transistors and they are realized under a 0.5um
technology, what transistor width Wn is required
for each case?
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-17. Find (a) operating point (b) small-signal
parameter gm (c) Rin,Rout,vL/vI (d) R3(MAX)
10-19. Find (a) operating point {VGS, ID, VDS} (b)
gm and rDS (c) Rin , Rout, and vL/vI
Answers:
(a) {2.0V, 0.25mA, 7.0V},
(b) 0.5mA/V
(c) 250k, 30k, -8.0 V/V
(d) 52 k
Answers:
(a) {-2.0V, 0.5mA, -2.0V},
(b) 1.0mA/V, 200 k
(c) 240 k, 11.32k, -9.52 V/V
10-20. Find (a) operating point {VGS, ID, VDS} (b)
gm and rDS (c) Rin , Rout, and vL/vI . All resistances
are in k unless otherwise indicated.
10-18. Find (a) operating point (b) small-signal
parameter gm, r0, rout (c) Rin,Rout,vL/vI (d)
R3(MAX). All resistances are in k unless
otherwise indicated.
Answers:
(a) {-2.5V, 0.5mA, 1.5V},
(b) 2mA/V, 400 k
(c) 300k, 9.52k, -7.5 V/V
(d) 12 k
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-21. Find (a) operating point (b) small-signal
parameter gm , gD (c) Rin,Rout ,vL/vI . Resistances
5in k unless otherwise indicated.
10-23. Synthesize CMOS single-level realizations
for each of the following logic functions. Show
K-maps and (Boolean) algebraic form and
synthesize with a minimum number of transistors.
(a) F(A,B) = XNOR(A,B)
(b) F(a,b,c,d) = ab  ad  bc
(c) F(a,b,c,d) = m(0,1,4,5,6,10,11,12,14,15)
(d) F(A,B,C,D) = m(2,3,7,8,9,13)
(e) F(a,b,c,d) = m(0,2,3,4,6,8,10)
(f) F(A,B,C) = Majority(A,B,C)
(g) F(w,x,y,z) = m(0,1,2,6,8,10,14)
10-24. Assume a 2.5 volt technology (V+ =
2.5V) and determine VIT and IMAX for the following
CMOS inverter transition characteristics as
reduced by second-order effects
Answers:
(a) {-2.0V, 3.0mA, 6.0V},
(b) 10.9mA/V, 0.03 mA/V
(c) 500k, 0.088k, 0.94 V/V
(a) KN = KP = 20A/V2, VTN = -VTP = 0.7
(b) KN = 20A/V2, KP = 10A/V2, VTN = -VTP =
0.6V
(c) KN = KP = 20A/V2, VTN =0.8V,VTP.= -0.5V
10-22. Find (a) operating point (b) small-signal
parameter gm , gD (c) Rin,Rout,vL/vI
Answers: (a) 1.25V, 6.05uA (b) 1.14V, 5.8uA.
10-25. Determine the effect of V+ on CMOS
dynamic power contributions PTRAN and PQ (in
W) and dynamic currents ITRAN and IQ (in
nA/MHz) for a CMOS technology for which VTN =
-VTP = 0.6V and KN = KP = 25 A/V2 (as reduced
by second-order effects) Assume average toggle
frequency f = 400MHz, transition time t = 0.05ns
and capacitance load CL = 5.0 fF.
(a) V+ = 3.2V
(b) V+ = 2.2V
Answers:
(a) 1.6W, 20.5W, 1.25nA/MHz, 16nA/MHz.
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-26. For most logic circuits, bit information is
stored as charge and voltage on a capacitance as
represented by figure C-7. Switch SW1 closure
transfers charge to/from the input of the CMOS
logic gate.
10-27. Similar to the previous problem, assume
that capacitance C1 is charged low and contains
"bit" charge at 0.2V. It is used to toggle a CMOS
inverter, (which will then execute other logic
commands further down the line).
Assume that the input capacitance Cin to the
inverter, in this case, is 20 fF and is initially at VG
= 2.7V, for which Vout = VOL = GND. After the
switch SW1 closes, the charge on C1 and Cin will
redistribute, a new voltage will appear at the gate,
and Vout will rise. Assuming a 3V technology, (V+
= 3.0V) and thresholds, as indicated, determine:
Assume Cbit = 36fF at Vbit = 3.0V and sum of gate
capacitances = 9fF. Assume VG = 0.0V for which
Vout = V+.
After switch SW1 closes, the charge will
redistribute, VG will increase and Vout will go to a
lower value.
(a) The value of VG due to charge
redistribution that will result after the switch
closes.
(b) The initial pull-up current (due to pull-up
transistor MP) at Vout when the voltage VG is
suddenly applied to the gate and Vout is still
lingering at GND.
(c) The pull-up current Iup when Vout is
increasing but is momentarily at Vout = 1.0V. This
pull-up current = IP - IN.
(d) The value of Vout at equilibrium (t =
infinity) for which IN and IP balance out.
Determine this level of current (for which I = IN =
IP ).
Assuming a (V+ = ) 3.6V technology determine:
(a) The value of VG after SW1 closes.
(b) The initial pull-down current (due to MN)
at Vout when new VG is suddenly applied to the gate
and Vout is still lingering at V+.
(c) The pull-down current when Vout is
decreasing but momentarily at 2.0V. This current
is call I(pull-down) and IPD = IN - IP.
(d) The value of Vout at equilibrium (for which
IN = IP), and the value of this current.
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Analytical exercises, Circuits, Devices, Networks and Microelectronics
10-28 A 0.4m, 2.0V CMOS logic technology
(i.e. gate length L = 0.4m and V+ = 2.0V) has tOX
= 8.63nm. It is used in a logic gate for which the
nMOS and pMOS transistors have WN = 1m and
WP = 2m, respectively. The logic gates are
toggled (on the average) at a frequency of
200MHz. Determine:
(a) CL = (2/3) x sum of gate capacitances of
the nMOS and pMOS transistors.
(b) Dynamic power PQ (W) used by one
gate.
(c) If each gate takes up a footprint space of
6m x 4m, how many gates can be mounted on
the cross-section of a human hair that is 40m in
diameter?
(d) If each hair uses (on average) 2 crosssections in which logic gates are inserted, then
how much dynamic power is dissipated in each
hair and how much current flows through each
hair?
(e) If each wig has 100,000 hairs, how much
(dynamic) power is used by each wig?
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