list - Lehrstuhl für Technische Elektronik

Themenliste für das/Topics for
Hauptseminar Technische Elektronik/
Seminar on Topics in Integrated Systems Technology
Sommersemester 2015
All topics are offered in German or English
T1: Comparison of Direct Up-Conversion and Polar
Transmitter Architectures for Cellular Wireless
Communications
One of the major topics in semiconductor companies for the next years is the Internet
of Things, enabling more and more devices to communicate with each other.
Depending on the requirements on data rate, mobility, etc., different communication
standards as WiFi, Bluetooth or cellular communication (e.g. GSM, UMTS, LTE) are
used. As many devices are portable and run from batteries, their mobile
communication transceivers implementing these functionalities are key components
and have to be highly integrated circuits with strong requirements on wireless
performance and power consumption.
At the moment two major transmitter architectures are used for all of these standards:
direct up-conversion transmitters, based on I/Q modulators, and polar transmitters,
based on polar modulators [1, 2]. I/Q modulators use directly the I and Q parts of the
transmit symbol to form the output waveform, whereas the polar modulators use
magnitude and phase information calculated from the I/Q symbols. Both have
advantages and disadvantages, depending on the communication standard(s)
implemented and the general requirements of the manufacturer on the device in
which they are used.
The goal of this work is to give an introduction to both transmitter architectures and to
discuss them under the aspect of complexity and wireless performance.
[1]
[2]
J. Groe, “Polar transmitters for wireless communications,” Communications Magazine, IEEE,
vol. 45, no. 9, pp. 58–63, 2007.
Sowlati, T.; Rozenblit, D.; Pullela, R.; Damgaard, M.; McCarthy, E.; Dongsoo Koh; Ripley, D.;
Balteanu, F.; Gheorghe, I., "Quad-band GSM/GPRS/EDGE polar loop transmitter," Solid-State
Circuits, IEEE Journal of , vol. 39, no. 12, pp.2179,2189, Dec. 2004
T2: High Density Flash Architectures
The ongoing evolution of mobile applications requires ever increasing amounts of
non-volatile memory. NOR flash usually is used for code storage that requires
execute in place (XIP) operation, whereas NAND flash allows higher memory density
and throughput at higher latency for big data storages. Since both topologies are
facing their limits when shrinking further, new architectures have to be found that
overcome the issues. Lithographic bounds, break down issues, coupling problems
and other difficulties, that arise when memory is packed more densely, have to be
faced by novel approaches.
Search for innovative flash memory technologies presented in literature and give an
overview of the most promising ones. Include NOR as well as NAND architectures
and highlight their benefits and challenges.
Lots of publications on that topic can be found in the IEEE Xplore database. Here are
some examples:
[1]
[2]
[3]
[4]
De Vos, J. et al., ”A scalable Stacked Gate NOR/NAND Flash Technology compatible with
high-k and metal gates for sub 45nm generations.”, IEEE International Conference on
Integrated Circuit Design and Technology (ICICDT), 2006
Kadowaki, T. et al, “A New Architecture for High-Density High-Performance SGT NOR Flash
Memory”, IEEE Transactions on Circuits and Systems, 2008
Yoon, K. et al., “A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical NOR Array
Structure”, IEEE Transactions on Nanotechnology, 2010
Eun-Seok, C., “A Novel 3D Cell Array Architecture for Tera-bit NAND Flash Memory”, IEEE
International Memory Workshop (IWM), 2011
T3: DC-DC converter: control techniques for high efficiency
step-down converters (in English)
The reduction of the size of the IC and the increasing trend towards system-on-chip
applications, such as portable electronic products (PDA, digital camera, MP3 player
etc.) lead the designers to include many more functional modules. Therefore there is
an overall increase in the power consumption of the systems. Since this trend runs
parallel to the lowering of the power supply of the ICs, battery-powered products
need highly efficient voltage conversion circuits (step-down conversion from Vbat to
Vdd) to affect the battery life as little as possible. Linear power regulators cannot be
used because they can handle only low power levels and voltage difference between
input and output since they waste energy according to the power difference into heat.
Consequently, high-efficiency switched-mode DC-DC converters, employing
semiconductor power switches, have been developed rapidly in recent years. For
many applications like cell phones, sensors etc., the system works under heavy-load
only during the issued task, and then it works most of the time under light-load
condition (standby). Therefore the optimization of this working condition is becoming
a dominant concern in the field of DC-DC design; especially for low power
implementations the simplicity and efficiency of the implementation of the control
circuitry is a key feature.
The aim of this seminar topic is to investigate and analyze some of the most efficient
solutions presented in literature (or even from the industry field) and compare the
advantages and disadvantages of the different approaches.
T4: Time Dependent Dielectric Breakdown (TDDB) in high-k
CMOS Technologien
Eine der größten Herausforderungen beim Design von CMOS RF-Schaltungen in
high-k Technologien sind die niedrigen Versorgungsspannungen im Bereich von 1V.
Dadurch können viele Systemanforderungen von RF-Schaltungen wie etwa die
maximale Ausgangsleistung eines Leistungsverstärkers nicht erfüllt werden. Daher
werden CMOS RF-Schaltungen in vielen Fällen bei Versorgungsspannungen, die
höher als die nominale Versorgungsspannung sind, betrieben. Dies führt einerseits
zu
einer
beschleunigten
Alterung
der
Schaltung
durch
klassische
Degradationsmechanismen wie BTI (Bias Temperature Instability) oder HCI (Hot
Carrier Injection), deren Auswirkungen auf die Schaltungsperformance meist jedoch
tolerierbar sind. Daneben besteht jedoch vor allem die Gefahr eines GateDurchbruchs (TDDB), der nicht toleriert werden kann, da dieser unmittelbar zu einem
Ausfall der betroffenen Schaltung führt.
In diesem Hauptseminar sollen zunächst die physikalischen Ursachen von TDDB in
high-k Technologien anhand aktueller Publikationen erarbeitet werden. Ein weiterer
Schwerpunkt liegt auf der Gegenüberstellung der unterschiedlichen Messmethoden
für TDDB, unter anderem für DC/AC und RF-Stresstests. Abschließend soll die
Abhängigkeit des TDDB von der Frequenz und die sich daraus ergebende
Schlussfolgerung für den Betrieb von RF-Schaltungen herausgearbeitet werden. Für
die Bearbeitung dieses Themas ist sowohl das Verständnis von als auch das
Interesse an komplexen physikalischen Vorgängen in CMOS Transistoren
notwendig.
T5: Fault Tolerance in Multi-Processor-System-On-Chips
(MPSoC’s)
The feature size shrinkage in modern CMOS technology increases the occurrence of
permanent and transient physical failures = faults in circuit operation. These reliability
problems make dependability and fault tolerance one of the major challenges of
future technologies. Production lines of major manufacturers already include means
to tolerate single defective cores in MPSoC’s (Multiprocessor System-on-Chip),
where multiple individual processors (or processor elements) can be used in parallel.
An important issue is to find an appropriate compromise between the reliability
enhancement and complexity overhead as well as the power consumption of such
solutions. Non-critical systems may tolerate a specific degree of transient
unavailability and/or performance-degradation, allowing the system to take adaptive
strategies that attempt repairing/fixing means before flagging units as faulty.
The aim of this topic is to investigate and analyze some of the existing solutions to
deal with faulty and defective components in MPSoC’s and to compare their
advantages and disadvantages.
[1]
[2]
[3]
J. H. Collet, P. Zajac, M. Psarakis and D. Gizopoulos, “Chip Self-Organization and Fault
Tolerance in Massively Defective Multicore Arrays”, In: IEEE Transactions on Dependable and
Secure Computing, Vol. 8, No. 2, DOI: 10.1109/TDSC.2009.53, pp. 207-2017, 2011
N. Hébert, G. M. Almeida, P. Benoit, G. Sassatelli and L. Torres, “A cost-effective solution to
increase system reliability and maintain global performance under unreliable silicon in
MPSoC“, In: Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig), DOI:
10.1109/ReConFig.2010.43, pp. 346 - 351, 2010
E. Wachter, A. Erichsen, L. Juracy, A. Amory and F. G. Moraes, “A Fast Runtime Fault
Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications”, In:
27th Symposium on Integrated Circuits and Systems Design (SBCCI), DOI:
10.1145/2660540.2660986, pp. 1-7, 2014
T6: Low Power Circuit Design with Tunneling Field Effect
Transistors (TFETs) (in English)
As MOSFET devices get smaller, certain fundamental limits to the technology are
being reached. One of the more promising technologies to replace traditional
MOSFETs are TFETs. TFETs work using a different operating principle than
MOSFETs and can overcome many of the technological issues currently affecting
circuit design. At its simplest level, a TFET works by controlling the amount of current
that can quantum mechanically tunnel through the device. This tunneling current
promises benefits such as operating at very low voltages, reduced leakage currents,
and offers the possibility to implement the n-type and p-type devices for
complementary logic with the same device!
Of course, TFETs are not a silver bullet and come with their own issues. The
traditional SRAM design does not function well with TFETs and inverters do not have
rail-to-rail behaviour. Despite these and other issues, this technology promises
benefits theoretically impossible for MOSFETs as long as we use the TFETs in our
design properly.
This seminar topic will look into the advantages and disadvantages of TFETs
compared to MOSFETs and how these affect design decisions in TFET circuits.
T7: TFET Technology
Tunnelling Field-Effect Transistors (TFET’s) have recently gained a lot interest due to
their ability to save a lot of power in electronic circuits. The inverse subthreshold
slope in a commonly used MOSFET is physically limited to a minimum value of
60mV/dec. This limitation prevents further downscaling of the supply voltage in order
to reduce power consumption in electronic circuits. In theory, TFET’s can have an
inverse subthreshold slope smaller than 60mV/dec and therefore are a potential
replacement for MOSFET’s in low-power applications. The structure of a TFET is
similar to a MOSFET except for the doping of drain and source. This fact allows an
easy integration in a well-known CMOS process but experimental results show that it
is difficult to reach sufficiently high currents with an inverse subthreshold slope
smaller than 60mV/dec. Therefore new technology concepts and materials have to
be explored to fabricate competitive TFET devices.
This seminar topic should give an overview of current technologies and material
systems used to produce TFET’s. Different concepts should be compared not only in
respect to high on-state currents and high subthreshold slopes but also the
compatibility to integrate the technology in a commonly used state-of-the-art CMOS
process should be investigated.
[1]
[2]
[3]
[4]
[5]
A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,”
Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010.
U. Avci, M. Daniel, and I. Young, “Tunnel Field-Effect Transistors: Prospects and Challenges.”
Q. Zhao, S. Richter, C. Schulte-Braucks, L. Knoll, S. Blaeser, G. Luong, S. Trellenkamp, A.
Schaefer, A. Tiedemann, K. Bourdelle, and others, “Strained Si and SiGe Nanowire Tunnel
FETs for Logic and Analog Applications.”
A. Seabaugh, “Fundamentals and current status of steep-slope tunnel field-effect transistors,”
in Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European,
2011, pp. 34–35.
A. M. Ionescu, H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches.”
Nature 479, 329–337 (17 November 2011) doi:10.1038/nature10679
T8: Effect of sputtering parameters on the electrical,
structural, and morphological properties of ultra-thin
magnetic films
Nanomagnetic logic (NML) is a very promising approach for future data storage,
digital logic and data processing. It offers outstanding properties such as
nonvolatility, low power operation, compatibility to existing CMOS manufacturing
processes and small footprint. The functionality of NML is based on magnetostatic
interaction of bistable nano-scale ferromagnets. The nonvolatility of NML allows to
move away from Von-Neumann-based computing to new paradigms of data
processing.
Many state of the art magnetic devices in research and industry are based on ultrathin multilayer ferromagnetic films with perpendicular magnetic anisotropy (PMA),
e.g. HDDs, GMR sensors as well as magnetic memory and in future maybe also
logic. The quality of such ultra-thin films is crucial for the correct and reliable function
of magnetic logic and memory devices. Therefore it is important to study the effect of
the sputtering parameters on the morphological, structural, and electricalproperties
of ultra-thin films.
The paper shall give an overview of key sputtering parameters and their impact on
ultra-thin magnetic multilayer film. The focus should lay on initial and working
pressures as well as on sputtering power using radio frequency (RF) magnetron
sputtering technique to deposit ultra-thin Co/Pt and Co/Ni multilayer films.
[1]
[2]
[3]
M. Becherer et al., "Towards on-chip clocking of perpendicular Nanomagnetic Logic", SolidState Electronics, vol. 102, 2014, doi:10.1016/j.sse.2014.06.012.
Mattox, Chapter 7 - Physical Sputtering and Sputter Deposition (Sputtering), In Handbook of
Physical Vapor Deposition (PVD) Processing (2ed Edition), William Andrew Publishing,
Boston, P. 237-286, ISBN 9780815520375 2010, http://dx.doi.org/10.1016
Carcia P.F. et al., Effect of sputter-deposition processes on the microstructure and magnetic
Properties of Pt/Co multilayers. Journal of Magnetism and Magnetic Materials 121 (1993) 452460.
[4]
[5]
Carcia, P.F. et al., Sputtered Pt/Co multilayers for magneto-optical recording, Magnetics,
IEEE Transactions on (Volume:26 , Issue: 5 ), 1990, DOI:10.1109/20.104498.
Wasa, K.: Handbook of Sputter Deposition Technology. William Andrew (Elsevier),
2nd edition, 2012.
T9: Resolution Enhancement Techniques
Als ‘Resolution Enhancement Techniques‘ (RETs) werden Methoden zur Erhöhung
der Auflösung in der optischen Lithographie für die Herstellung integrierter
Schaltkreise bezeichnet. Dabei steht als Motivation die Aufrechterhaltung des von
Moore vorhergesagten Skalierungstrends für die CMOS-Industrie im Vordergrund.
Alternative Verfahren zur optischen Lithographie, wie z.B. die EUV Lithographie
haben aufgrund höherer Kosten und geringerer Ausbeute noch keinen Einzug
gefunden. Im Vergleich dazu sind die eingesetzten RETs kostengünstiger und
erlauben eine Auflösung unterhalb der Wellenlänge der verwendeten Lichtquelle.
Zu diesen Techniken gehört unter anderem der Einsatz sog. PhasenschieberMasken (Phase Shift Mask), die optische Nahbereichskorrektur (Optical Proximity
Correction), Mehrfachstrukturierung (Double Patterning), Immersionslithographie
(Immersion lithography), etc.
In ihrer Arbeit und ihrem Vortrag sollen diese Techniken näher erläutert werden und
es soll auf zukünftige Entwicklungschancen der optischen Lithographie eingegangen
werden. Kann die optische Lithographie zusammen mit den eingesetzten RETs den
vorhergesagten Skalierungstrend weiterhin aufrechterhalten?
[1]
[2]
Liebmann, Lars W. "Layout impact of resolution enhancement techniques: impediment or
opportunity?." Proceedings of the 2003 international symposium on Physical design. ACM,
2003.
Ito, Takashi, and Shinji Okazaki. "Pushing the limits of lithography." Nature 406.6799 (2000):
1027-1031.

Download Report