LEIBNIZ-Konferenz Industrielle Revolution 4.0 im historischen Kontext Michael Raab „Technologie der Mikroelektronik der Schlüssel für die digitale Revolution“ Dresden, 19.März 2015 19. Leibnizkonferenz 1MDRAM Speicherchip aus Dresden Chipfläche 65.5mm2 AMD – Jerry Sanders „It is all about people“ First full functional 1MDRAM August 1988 Estimated number of produced parts in Dresden: 30kdice between Sept 1988 and 1990 Development without economical effect but LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 2 Technology 1MDRAM-1µm (1988) vs 32nm (2010) Scaling by factor of ~30 in 22years, 10Tech Nodes in between Si Substrate (125mm wafer) 16 mask layer (6 Implants) 1 Layer of Metal (Al/Si) SOI Substrate (300mm wafer) 55 mask layer (20 Implants) 11 Layers of Metal (Cu) Poly Silicon Gate HK Metal Gate MoSi Bitleitung 5th Gen Strained Silicon Gate Length: 1000nm Gate Length: 35nm DRAM Cell Size = 32.4µm2 SRAM Cell Size = 0.258µm2 LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 3 High Advanced Technologies in Dresden 2000 2002 2003 2004 2006 2008 2010 180nm 130nm 130nm 90nm 65nm 45nm 32/28nm Low-K dielectric SOI Immersion Lithography HKMG Cu Interconnect Strained-Si Multi-Strain Transistor 8 technologies successfully developed through Joint Development Alliance and AMD/GLOBALFOUNDRIES collaboration All technologies run in high volume manufacturing 32nm and 28nm volume manufacturing at GLOBALFOUNDRIES Cu Further scaling in GLOBALFOUNDRIES-Dresden only with EU and Germany funding, support and focus LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext Cu Pores in dielectric ULK 4 ITRS Roadmap 14nm 22nm 22nm 14nm 10nm 9nm 7nm 2011 2014 2016 2018 2019 2022 LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 5 From Bipolar to CMOS at highest performance 10µm 1µm 1013 Bipolar PMOS NMOS CMOS 1012 100nm Voltage Scaling 1011 Pwr Eff Scaling New Nanostructures GLOBALFOUNDRIES AMD 1965 Data (Moore) Memory Microprocessor 1010 Transistors/Die 10nm 109 108 AM/ZM Dresden 45nm 107 65nm 106 130nm 105 32nm ~ 1.4 – 1.5 billion transistors per die, 28nm ~ 9billion transistors per die, 450mm2 180nm 104 U61000 103 U264 102 dev U253 101 Source: Intel / P. Gargini ISS Europe 2009 D120 100 1960 1970 1980 1990 2000 2010 2020 LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 2030 6 Mikroelektronik Aufwand Cost Zusätzliche explosion forgezielte technology node Förderungen können 20nm, 14nm …. in Europe ermöglichen Intel/TSMC/Samsung/GLOBALFOUNDRIES/SMIC/UMC LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 7 TSMC Revenue to change from 28nm 20nm 10nm in 1H2016 1 year 28nm Don’t stop development followed by production LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext INTELs 14nm Technology with 2nd-Generation FINFET Self-Aligned Double Patterning, 0.0588µm2 SRAM cell size 4th generation high-k metal gate, and 6th-generation strained silicon Idsat improvement of 15% for NMOS and 41% for PMOS over 22nm 42nm fin and 70nm contacted gate pitch Idsat are 1.04mA/µm at Vdd 0.7V Slopes are maintained at ~65mV/decade; DIBL is ~60mV/V and ~75 mV/V for NMOS and PMOS, respectively IEDM2014 LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 9 Halbleitermarkt: das Herz für komplexe Systeme Datenverarbeitung ($ 455 Milliarden) Netzwerktechnik ($ 99 Milliarden) Medizintechnik ($ 173 Milliarden) Halbleiter Automobilelektronik ($ 100 Milliarden) ($333 Milliarden,) 2014, WSTS Mobilkommunikation ($ 223 Milliarden) Industrieelektronik ($ 318 Milliarden) Sector Market Size in US$ LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext Interposer or TSV Internationale Roadmap mit klaren System-Vorstellungen und 3D-Integration SoC auch mit Interposer oder TSV nur gemeinsam mit Basistechnologie möglich Handbook of 3D Integration: Volume 3 - 3D Process Technology Philip Garrou, Mitsumasa Koyanagi, Peter Ramm LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext Technology Summary enabling Industrial4.0 More Moore is now driven by Low-Power Product Smart System Integration Challenge for Technology scaling Semiconductor business enable growing markets Europe requires semiconductors to be competitive in Future and Industry 4.0 Semiconductor Production in Europe should be Industrial demand Dedicated Semiconductor Founding required LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext EU - Zielstellung EU-Ziel: 20% Mikroelektronik Fertigung in Europa bis 2020 Notwendiger Schritt zur Umsetzung Investition einer neuen 300mm Linie für 14…7nm Technologie in Europa LEIBNIZ-Konferenz, Industrielle Revolution 4.0 im historischen Kontext 13
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