DesignWare IP for Internet of Things Brochure

DesignWare IP
for IoT SoC Designs
The Internet of Things (IoT) is connecting billions
of intelligent “things” to our fingertips. The ability
to sense countless amounts of information that
communicates to the cloud is driving innovation
into IoT applications such as wearable devices
and machine-to-machine applications. Synopsys
provides a comprehensive portfolio of IP that
meets the specific requirements of IoT SoC designs
including silicon-proven interface IP and analog IP,
low-power embedded memories and logic libraries,
energy-efficient processor cores and integrated
subsystems.
Wearable devices
Machine to machine
Smart
appliances
Wearable
infotainment
Safety and
security
Smart cities
metering
Fitness
and health
Commerce
Figure 1: Examples of wearable devices and machine-to-machine applications
The “Thing” in Internet of Things
What’s Trending in Edge Devices
The Internet of Things is a vast array of applications starting from
Innovations are driving growth of the Internet of Things including
simple motion sensors and lighting systems to more advanced
the increase value of the information produced, longevity of battery
systems that require leading-edge control theory, rich graphic
operated devices, and low cost and easy–to-use methods to add
content and more. The Internet of Things is an extremely
connectivity to edge devices. The ability to process advanced sensor
fragmented market and can be defined as anything from sensors
algorithms and act upon that data in an efficient manner increases
to servers, which can include just about everything. If we take
the value of fitness and health and wearable infotainment as well as
a more pragmatic view, the increase in the number of “Things”
machine-to-machine applications. The efficiency advancements not
will come mainly from connecting both “brown field” (existing)
only improves the content of the data but also extends battery life.
and “green field” (new) “edge devices” to the internet. These are
The maturity of wireless technologies including Bluetooth Smart
devices that do the actual sensing, actuation and communicate
to hubs, concentrators, and aggregators, most commonly
used in commercial security systems, home routers, or mobile
phones.
(often known as Bluetooth Low Energy), WiFi, Zigbee, and other
competing 802.15.4 standards have helped clear the path to better
interoperability. Furthermore the technology alignment of IP in specific
process nodes help justify more advanced integration including the
Gartner estimates over 10 billion of these ”Things” will ship in 2020
advent of smart sensors and integration of high-performance analog
but only connected lights are expected to be more than 5% of that
and wireless connectivity. With the momentum around The Internet
number. This is just one illustration of the very fragmented set of
of Things, the investment, resources, and exposure available for edge
applications, all with very different design challenges.
device development has a direct impact on innovation.
To more effectively segment the IoT edge device market, it’s
The numerous applications within the IoT space make it difficult to
important to understand the system architectures, environment
identify common trends. However trends can be found in three
conditions, wireless connectivity needs and overall functions
common architectures. These architectures include application
offered to the end user. With these factors taken into consideration,
processors (high-end IoT), microcontrollers, (low-end IoT – MCU)
there are two main segments of edge device applications including
and smart analog, each with their own set of advantages.
wearable devices and machine-to-machine (See Figure 1). The
wearable device market includes applications such as wearable
infotainment and fitness and health. Machine-to-machine
applications consist of smart appliances, safety and security,
smart cities metering and commerce.
2
DesignWare IP for IoT SoC Designs
SoC
Logic libraries
Radio (WiFi, Bluetooth)
Display
MIPI
GPIO
SoC
LPDDR2/3
CPU
Ext flash
memory
controller
System logic
SD/eMMC
System logic
Sensor subsystem
Logic libraries
DesignWare IP
SRAM
ROM
Bluetooth
smart radio
Sensor subsystem
Customer/
3rd party IP
CPU
CPU
USB 2.0
host/OTG
I2C
· Gyroscope
SPI
ADC
Sensors
· Accelerometer
Touch/
gesture
· Compass
Figure 2: Example of high-end SoC block diagram
A system that requires a rich OS, such as Android and or Linux
typically requires external DRAM and a processor that supports
USB 2.0
host/OTG
Internal flash
I2C
SPI
SRAM
ROM
ADC
Touch/
gesture
DesignWare IP
Customer/
3rd party IP
Sensors
· Heart rate · Gyroscope · Accelerometer · Compass
Figure 3: Example of low-end MCU block diagram
Architecture Examples
The three architectures described above tend to be designed in
an MMU. These applications usually include vision, voice, audio,
lagging technology processes to save cost, power and leverage
and graphics functionality. Resource intensive communications
analog, wireless, and/or specialized memory integration. The
protocols also often outgrow the constraints microcontrollers
high-end applications processors (see Figure 2) are commonly
inherently have, forcing the use of high performance processor
being developed in 28-nm process technologies Many off-the-shelf
cores and external memory interfaces.
microcontroller solutions (see Figure 3) are available in 90nm but will likely
High-end system architectures leverage the system IP from SoCs
be migrating to 55-nm process technologies.
specifically designed for e-readers, tablets, and mobile phones and
Smart Analog solutions (see Figure 4) including power management
often do not meet the customers’ power or system cost requirements.
and sensors, 180nm is currently the process of choice, however,
Microcontroller architectures can be limited by the amount of on-chip NVM
will most likely migrate to more advanced nodes when it makes
and processing power available from the most popular processing cores.
sense.
This offers room for innovation for IoT-specific SoC and IP development.
A traditional microcontroller can fit into many IoT applications very
Radio (ISM, 802. 15.4, Bluetooth Smart)
effectively due to the low power design and integrated analog
functions. Furthermore, Non-Volatile Memory (NVM) often provides
efficient power budgets and lower system costs for edge devices.
Audio
System Logic
NVM
Finally, adding intelligence to a sensor application or other
Sensor subsystem
traditional analog function has traditionally incorporated an
additional microcontroller or applications processor.
Power
There is currently momentum around adding intelligent to
ARC EM
processor
MEMs sensors and power management devices by integrating
processing cores and NVM.
Sensor
I2C
SPI
SRAM/
ROM
DesignWare IP
Customer/
3rd party IP
ADC/
comparator
Figure 4: Example of smart analog SoC block diagram
DesignWare IP for IoT SoC Designs
3
DesignWare IP
SoC Impact
Thick oxide “always-on” logic
libraries
Provides the lowest leakage for always-on wakeup circuits during sleep states
Ultra-high density logic libraries
Multi-bit flip-flops
Power Optimization Kits (POKs)
6-track logic libraries optimize circuits for performance, power and area tradeoffs
Multi-bit flip-flops & pulse latches minimizes area and power consumptions
Power Optimization Kits (POKs) enable low power consumption, while sustaining optimal performance
STAR Memory System® (SMS)
Integrated test, repair and diagnostics: BIST for embedded Flash, an industry 1st
Memory compilers
Incorporates advanced power management features to reduce leakage by up to 70%, controlled via a single pin
via ROM
Ultra low-power anti-signature via ROM reduces leakage up to 20%
Sensor IP Subsystem
Delivers significant area savings with lower latency due to tightly coupled memory and sensor interface
peripherals as well as hardware accelerators to improve performance and reduce area
ARC EM processors
Power- & area-efficient processors based on extensible ARCv2DSP architecture. Ideal for deeply embedded
(microcontroller) applications including functions such as voice, sensor fusion and other complex algorithms
ARC HS processors
Delivers maximum performance efficiency (DMIPS/mW and DMIPS/mm2) for high-end IoT systems. Ideally
suited for embedded applications with high-speed data and signal processing requirements. Configurability
and extensible instruction set allows designers to tailor each processor instance for the optimum balance of
performance, power and area
NVM – Medium Density
Supports up to 64 KB to include most control algorithms & libraries including DSP, math, sensor fusion,
motor control, power conversion, security, touch, etc.
NVM – Ultra Low Power
Optimized for wireless applications such as RFID/NFC tags
NVM – Trim
Optimized for small area for sensors and analog ICs
NVM - EEPROM
High endurance EEPROM family delivers up to 1M write cycles
Analog-to-Digital Converters
ADCs with up to 16-bit resolution and 5 Msps conversion rates exceed leading on-chip implementations
USB 2.0
Certified USB 2.0 IP supporting host, device, OTG and Battery Charging with power down features
DDR
Delivers a complete multi-protocol DDR interface IP solution including LPDDR2, LPDDR3 and DDR3
SDRAM memories
MIPI
Compliant to MIPI CSI-2 specification rev 1.0. Supports 1 to 4 Rx data lanes with D-PHY PPI interface and
32-bit pixel output format
Accelerating Internet of Things SoC Designs
with Proven IP
1. Faster time to market
IP requirements for SoCs that go into IoT applications vary depending
3. Ability to evaluate cost & performance tradeoffs of building
on the specific application. Synopsys provides designers with a broad
an application from off the shelf components or investing in
portfolio of interface, embedded memory, logic library, processor and
ASSPs & ASICs.
2. Early software bring-up, debug and test
analog IP as well integrated IP subsystems to address the design needs of
high-end systems, low-end MCUs and smart analog SoCs. With support
In addition to the reference designs and development kits, Synopsys
for advanced features such as “always-on” logic libraries, multi-bit flip-flop
works closely with partners to ensure all the relevant software and
memory compilers as well as anti-signature ROMs and power efficient
tools needed to develop systems is available. This includes operating
processor architectures, Synopsys’ DesignWare® IP helps address the
systems, communication stacks, IDEs, client services, virtual
specific design challenges for the Internet of Things applications.
machines and much more.
IP Accelerated: Fast Prototyping, Software
Development, and Customized IP Subsystems
Summary
Prototyping and software development continues to be a large
improve the sensory and communications interfaces, Synopsys
portion of the total investment of designing an application for the
provides a broad portfolio of IP that is optimized for IoT and will help
Internet of Things. To significantly ease IP integration into SoCs and
you achieve your design goals faster and with significantly less risk.
Whether the goal is to provide reduce power, add connectivity, or
accelerate the software development effort, Synopsys provides
DesignWare IP Prototyping Kits, DesignWare IP Virtual Development
For more information on DesignWare IP for the Internet of Things,
Kits, and integrated IP subsystems as part of the IP Accelerated
visit: www.synopsys.com/ip-iot
initiative. This provides numerous benefits including:
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©2014 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
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08/14.RP.CS34785.

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