low dimensional simulator for carbon based devices

LOW DIMENSIONAL SIMULATOR FOR CARBON BASED DEVICES
NG CHIN LIN
UNIVERSITI TEKNOLOGI MALAYSIA
LOW DIMENSIONAL SIMULATOR FOR CARBON BASED DEVICES
NG CHIN LIN
A thesis submitted in fulfilment of the
requirements for the award of the degree of
Bachelor of Engineering (Electrical-Microelectronics)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
JUNE 2014
iii
Dedicated to my supervisor Dr Michael Tan Loong Peng, my fellow friends and my
endless support family
iv
ACKNOWLEDGEMENT
First and foremost, I would like to take this opportunity to pass my gratefulness
to my project supervisor, Dr. Michael Tan Loong Peng for his endless guidance and
supervision throughout the project period.
Secondly, I would like to thank my family especially my parents who always
give me their support either mentally or financial aspect throughout this whole year.
Last but not least, I would like to show my gratitude for those who has directly
and indirectly in lend me a hand during this project.
NG CHIN LIN, Skudai
v
ABSTRACT
Carbon-based devices such as carbon nanotube (CNT) and graphene
nanoribbon (GNR) have been explored rigorously as the potential successor
to conventional metal-oxide-semiconductor-field-effect-transistor (MOSFET). The
limitation of the silicon-based devices catalyst the break through research on carbonbased devices. In this research, a comprehensive quantum simulation tool based on
carbon devices is developed as graphical user interface (GUI) using MATLAB. In
particular, the quantum simulator is can be used for quasi-one-dimensional structure
namely CNT and GNR. The characteristic of the both carbon-based device is written
as MATLAB m-script file. The modeling approach is based on the work carried
out in Stanford University and the formalism is established on the top-of the barrier
approach from Purdue University. The interface of the GUI simulator is generated
using Graphical User Interface Development Environment (GUIDE) in MATLAB with
additional plug in. This simulation tool allows the user to trade off between precision
and time as it provide impromptu analysis either by graph or direct calculation
value. Furthermore, this simulator creates new platform for researchers to assess
the outcome of the carbon-based devices by either selecting their own specifications
or the default values. In addition, a reset action is provided to reduce the time
constraint for continuous benchmarking. Another features of this simulator is the
auto generation of the voltage transfer characteristic graph from the complementary
metal-oxide semiconductor (CMOS) drain characteristics. This simulator can operates
as standalone purpose software that is capable to function independently without the
installation of MATLAB. Nevertheless, this simulator is still at the preliminary stage
and it can be further improved by increasing its functionality and portability. This work
is as an ongoing development of the carbon-based device simulator in UTM.
vi
ABSTRAK
Peranti-peranti berasaskan karbon seperti karbon nanotube (CNT) dan
graphene nanoribbon (GNR) telah diterokai secara berterusan sebagai pengganti
berpotensi untuk metal-oxide-semiconductor-field-effect-transistor (MOSFET). Peranti berasaskan carbon diberikan keyakinan yang tinggi untuk mengatasi limit peranti
berasaskan silicon. Dalam kajian ini, alat simulasi kuantum yang komprehensif
untuk peranti berasaskan karbon akan direkakan dalam bentuk permukaan pengguna
grafik dengan mengunakan MATLAB. Khususnya, alat simulasi kuantum ini boleh
digunakan untuk kuasi satu dimensi struktur iaitu CNT dan GNR. Ciri-ciri kedua-dua
peranti yang berasaskan karbon akan dikodkan sebagai fail m-skrip dalam MATLAB.
Pendekatan model adalah berdasarkan kerja-kerja yang dijalankan di Universiti
Stanford dan formalism yang diwujudkan di bahagian atas di pendekatan halangan
dari University Purdue. Permukaan GUI simulator yang dihasilkan menggunakan
muka pengguna grafik persekitaran pembangunan (GUIDE) dalam MATLAB. Alat
simulasi ini membolehkan pengguna untuk mempertimbangkan di antara ketepatan
dan masa kerana ia menyediakan analisis secara langsung dengan graf atau jawapan
pengiraan secara langsung. Tambahan pula, simulator ini mewujudkan platform baru
bagi penyelidik untuk menilai hasil daripada peranti yang berasaskan karbon dan
ciri-cirinya dengan memilih sama ada spesifikasi mereka sendiri atau nilai lalai. Di
samping itu, tindakan set semula disediakan untuk mengurangkan kekangan masa
untuk penandaarasan secara berterusan. Ciri-ciri lain simulasi ini adalah dalam
penjanaan graf ciri-ciri pemindahan voltan secara auto daripada semikonduktor oksida
logam pelengkap (CMOS) drain characteristik. Alat simulasi ini boleh beroperasi
sebagai perisian bebas yang mampu berfungsi secara bebas tanpa pemasangan
MATLAB. Walau bagaimanapun, alat ini adalah masih di peringkat awal dan ia
boleh lagi diperbaiki dengan meningkatkan fungsi dan kemudahannya. Kerja-kerja ini
adalah sebagai satu pembangunan yang berterusan daripada peranti berasaskan karbon
simulasi di UTM.
vii
TABLE OF CONTENTS
CHAPTER
TITLE
DECLARATION
DEDICATION
ACKNOWLEDGEMENT
ABSTRACT
ABSTRAK
TABLE OF CONTENTS
LIST OF TABLES
LIST OF FIGURES
LIST OF ABBREVIATIONS
LIST OF SYMBOLS
LIST OF APPENDICES
1
INTRODUCTION
1.1
Background
1.2
Problem Statement
1.3
Objectives
1.4
Research Scope
1.5
Market Analysis
1.6
Contribution
2
LITERATURE REVIEW
2.1
The Fundamental of MOSFET
2.1.1
Basic of MOSFET
2.1.2
Structure of MOSFET
2.1.3
Operation of MOSFET
2.1.4
Liner mode
2.1.5
Saturation Mode
2.1.6
Velocity Saturation
2.1.7
Limitation of Silicon Technology
PAGE
ii
iii
iv
v
vi
vii
x
xi
xiv
xvi
xvii
1
1
2
2
3
3
5
6
6
6
7
8
8
9
10
11
viii
2.2
2.3
2.4
2.5
Graphene
2.2.1
Graphene Nano Ribbon (GNR)
Carbon Nanotube (CNT)
2.3.1
Operation of CNTFET
Device Model
2.4.1
Non-equilibrium
Green’s
function
(NEGF)
2.4.2
Top-of-the-barrier (TOB)
Existing Simulator
2.5.1
NEMO-VN1
2.5.2
Quantum Wise
2.5.3
Purdue Nano-hub (FETToy)
12
12
14
15
16
16
17
21
21
22
22
3
RESEARCH METHODOLOGY
3.1
Introduction
3.2
Methology Work Flow
3.3
Device Modeling
3.4
MATLAB
3.4.1
MATLAB GUIDE
24
24
25
26
26
26
4
RESULT AND DISCUSSION
4.1
Introduction
4.2
LODISI
4.2.1
LODISI Function Button
4.2.2
Graph Option and Metric Performance
4.2.2.1 Drain Current versus Drain
Voltage Characteristic
4.2.2.2 Drain Current versus Gate Voltage Characteristic
4.2.2.3 Mobile Charge versus Gate
Voltage Graph
4.2.2.4 Average Velocity versus Gate
Voltage Graph
4.2.2.5 Mobile Charge versus Drain
Voltage Graph
4.2.2.6 Quantum Capacitance versus
Gate voltage Graph
28
28
28
31
32
33
35
37
37
38
39
ix
4.2.2.7
4.2.3
4.2.4
Nmos-Pmos Field-effect Transistor Plot (NP-FET)
4.2.2.8 Voltage Transfer Characteristic
(VTC)
LODISI GNR
Standalone Software
40
42
44
45
5
PROJECT MANAGEMENT
5.1
Introduction
5.2
Project Schedule
5.3
Cost Estimation
46
46
46
48
6
CONCLUSION
6.1
Future Work
49
49
REFERENCES
Appendices A – B
50
53 – 54
x
LIST OF TABLES
TABLE NO.
4.1
4.2
5.1
5.2
TITLE
The input parameter and default value for the LODISI CNT
and LODISI GNR
List of plot options and metric performance of LODISI
Project Gantt Chart (Semester One)
Project Gantt Chart (Semester Two)
PAGE
31
33
47
47
xi
LIST OF FIGURES
FIGURE NO.
1.1
1.2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.17
TITLE
Research and technology development schedule proposed for
carbon based nanoelectronic to impact industry’s timetable
(Taken from ITRS 2009)
Percentage of simulation user for FETToy from 2003 until
2013 (Taken from [1])
The MOSFET structure (Taken from [2])
The front view MOSFET structure (Taken from [2])
Transistor level and front view of the PMOS and NMOS
(Taken from [3])
Liner mode (Taken from [4])
Saturation mode (Taken from [4] )
Velocity Saturation (Taken from [4])
Graphene able to construct three different carbon allotropes
which are buckyball, carbon nanotube and graphite(Taken
from [5])
Armchair and zigzag GNRs with lines N and width W (Taken
from [6])
Proposed GNRFET structure
Single-wall carbon nanotubes (SWNT)
Multi-wall carbon nanotubes (MWNT) with three shells
The three configuration of CNT: (a) armchair (b) zigzag (c)
chirality
Schcottky barrier CNTFETs (Taken from [6])
General matrix model for nanoscale device connected to two
contacts.(Taken from [6])
Population of k-states at equilibrium at the top-of-the-barrier
(Taken from [6])
Population of k-states at non-equilibrium at the top-of-thebarrier (Taken from [6])
PAGE
4
4
7
7
8
9
10
11
12
13
13
14
14
15
16
17
18
19
xii
2.16
2.18
2.19
2.20
2.21
3.1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
A generic circuit model for ballistic transistor (Taken from
[6])
Self consistent solution for USC and carrier density N (Taken
from [6]) Therefore, top-of-the-barrier approach is much
easier compare the NEGF method
The layout of the CNT simulator of NEMO-VN1 (Taken from
[7])
Atomistix ToolKit(ATK) (Taken from [8] )
FETToy simulator layout for Silicon Nanowire MOSFET
(Taken from [1])
The flow chart of the project
The main interface of LODISI
The interface for the LODISI CNT
The simulator window for LODISI GNR
Drain current versus drain voltage of a n-type CNTFET using
the default parameter in tabulated in Table 4.1
Drain current versus drain voltage of a p-type CNTFET using
the default parameter in tabulated in Table 4.1
Drain current versus gate voltage for n-type GNRFET with
default parameters
Semilog plot of drain current, IDS against gate voltage, VG
for the default parameters of n-type GNRFET
Mobile charge versus gate voltage for the n-type CNTFET
with default parameters
Average velocity versus gate voltage for the n-type CNTFET
with default parameters
Mobile charge versus drain voltage for the n-type CNTFET
with default parameters
Quantum capacitance versus gate voltage for the n-type
CNTFET with default parameters
I-V characteristics for n-type (green line) and p-type (blue
line) CNTFET for VG = 0 V to 1 V (bottom up) in 0.0526 V
spacing. The red dashed line represents the drain current in
the CNT-based CMOS inverter
I-V characteristics for n-type (green line) and p-type (blue
line) GNRFET for VG = 0 V to 1 V (bottom up) in 0.0909 V
spacing. The red dashed line represents the drain current in
the GNR-based CMOS inverter
19
20
21
22
23
25
29
30
30
34
35
36
36
37
38
39
40
41
42
xiii
4.14
4.15
4.16
4.17
Voltage transfer characteristic for an almost symmetrical IV for n-type and p-type CNTFET with source fermi energy,
EF = -0.32 eV (n-type) and 0.32 eV (p-type)
The VTC graph of asymmetrical I-V for n-type CNTFET with
EF =-0.32 eV and p-type CNTFET with EF =0.64 eV PMOS
“Wrong Chirality number. Now it is metallic” will be
shown in the warning panel when the wrong chirality number
inserted
LODISI window standalone application
43
44
45
45
xiv
LIST OF ABBREVIATIONS
CNT
–
Carbon Nanotube
GNR
–
Graphene Nanoribbon
MOSFET
–
Metal Oxide Semiconductor Field-Effect Transistor
CNTFET
–
Carbon Nanotube Field-Effect Transistor
GNRFET
–
Graphene Nanoribbon Field-Effect Transistor
LODISI
–
LOw DImensional SImulator
GUIDE
–
Graphical User Interface Deveplopment Environment
CMOS
–
Complementary Metal Oxide Semiconductor
UTM
–
Universiti Teknologi Malaysia
MATLAB
–
Matrix Laboratory
GUI
–
Graphical User Interface
Q1D
–
Quasi One Dimensional
VTC
–
Voltage Transfer Characteristic
NMOS
–
n-channel MOSFET
PMOS
–
p-channel MOSFET
MOS
–
Metal Oxide Semiconductor
AGNR
–
Armchair Graphene Nanoribbon
ZGNR
–
Zigzag Graphene Nanoribbon
2D
–
Two Dimensional
1D
–
One Dimensional
3D
–
Three Dimensional
SWNT
–
Single-wall carbon nanotubes
MWNT
–
Multi-wall carbon nanotubes
SB-CNTFET
–
Schottky-barrier Carbon Nanotube Field-Effect Transistor
NEGF
–
Non-Equilibrium Green’s Function
FETToy
–
Field Effect Transistor Toy
NP-FET
–
NMOS-PMOS field-effect transistor
I-V
–
Current Voltage
xv
SS
–
Subthreshold Swing
DIBL
–
Drain-Induced Barrier Lowering
–
xvi
LIST OF SYMBOLS
=
–
Fermi Dirac integral Function
p+
–
High Positively doping
n+
–
High Negatively doping
SiO2
–
Silicon oxide
VG
–
Gate Voltage
VGS
–
Gate-Source Voltage
VT H
–
Threshold Voltage
VT
–
Threshold Voltage
VDS
–
Drain-Source Voltage
ID
–
Drain Current
VDS(SAT )
–
Saturation Drain-Source Voltage
VS
–
Source Voltage
VG
P
–
Gate Voltage
n
–
Self-energy matrix
VSC
–
Sefl-consistent Voltage
VL
–
Low potential
VP
–
Barrier potential
IDS
–
Dain-Source current
GON
–
ON-conductance
EF
–
Fermi Energy
KB
–
Bolztman constant
T
–
Temperature
q
–
Electron
ION
–
On current
IOF F
–
Off current
–
xvii
LIST OF APPENDICES
APPENDIX
A
B
TITLE
NP-FET
VTC
PAGE
53
54
CHAPTER 1
INTRODUCTION
1.1
Background
In twenty-first century, electron gadgets have become part and parcel in human
life. The performance and functionality of the electronic gadgets required by people
increase from time to time. Everything has its own limitation including the silicon
based transistor. The limitation of the silicon based transistor technology is hard
to fulfil people’s requirement for the coming future. Hence, a better material based
transistor needed to replace the current technology. In 2004, a miracle material which
can revolutionize the entire electronic technology had came to the world. Two great
physicist Andre Geim and Kostya Novoselow won the 2010 Nobel Prize for Physics
after discovered this substance [9]. It was graphene - a one atom thin substance with
superior electrical properties.
After this great discovery, scientist around the world profusely carried out the
research on this material and keep on researching its possibility to break through
the limit of silicon based transistor. The discovery of graphene has climbed into
new level in advanced technology which enables scientists and engineers to expand
their innovation and create new products. Since graphene has been introduced into
semiconductor industry, it gives significant contribution to the CMOS architecture
and other devices. Graphene forms graphene nanoribbons (GNRs) and carbon
nanotubes (CNTs) in which both of the allotropes give promising electronic and
thermal properties in CMOS architecture especially in gate channel. Thus, this new
material enables CMOS to push its technology beyond limits. Hence, carbon based
device transistors-carbon nanotube and graphene nanoribbon field-effect transistor
were created. Nevertheless, these devices still require ample of research to make it
possible in commercialise product.
2
Therefore, a comprehensive and simple simulation tools is essential to boost up
the speed of research for carbon based device. An accurate and easy to use simulation
tools will help those scientists and researchers on their finding. Indirectly, this can help
on the development of carbon based devices in the CMOS architecture.
This research is on a quantum simulation tools for carbon based devices. The
graphical user interface (GUI) simulator is designed by using MATLAB and m-script
file. The quantum simulator tools include the graphene nanoribbons and carbon
nanotube field-effect transistor. This quantum simulator allow the user to trade-off
between accuracy and speed. With this simulation tools, researcher can predict, project
and benchmark their model by inserting their own specification in this GUI simulator.
1.2
Problem Statement
Common MOSFET will reach its physical limits soon when the channel length
reached to about 10nm. As the matter of fact, conventional MOSFET is no longer
be used to develop future electronic devices. Therefore, to study the capabilities and
investigate the electrical properties of a quasi one-dimensional (Q1D) nanostructure of
carbon based devices, a simulation tools is one of the key factor for this development.
As silicon-based will soon face its limit due to Moore’s Law. As a results, an easyto-use device simulator with good accuracy is significant for fast computation and
projection will be developed in MATLAB. A simulation tool is needed for researcher
to predict, project and benchmark their model by inserting their specification input
in a GUI simulator to generate a wide of electrical properties such as drain and gate
characteristics.
1.3
Objectives
This project objective is to create a graphical user interface simulation tools
to study the electrical properties for graphene nanoribbon and carbon nanotube fieldeffect transistor.
•
To create a new platform to investigate the electrical properties of a quasi
one-dimensional (Q1D) nanostructure for carbon-based devices namely carbon
nanotube (CNT) and graphene nanoribbon (GNR) field-effect transistor (FET).
3
•
To create a user friendly graphical user interface simulator in MATLAB that
enable parameter entry, calculation control, graphical result display for data
projection and on the spot analysis.
•
To compute drain-induced barrier lowering, sub threshold swing and on-off
current ratio from the gate characteristic of these model instantly.
1.4
Research Scope
This simulation tool is designed by using MATLAB GUI with the top-of-the
barrier approach. MATLAB GUIDE is used to design the interface of the simulator
and interconnect with the created algorithm in the m-script file. Some additional
plug-in for the MATLAB GUIDE are consider to improve the visual appearance of
the simulator. Currently, this simulator only function for graphene nanoribbon and
carbon nanotube field-effect transistor. The circuit performance of these carbon based
devices will simulated in graph impromptu when user inserting the parameters like
channel length, gate thickness and others. Furthermore, the simulator tools act as a
computational calculator to calculate the threshold voltage, sub-threshold swing and
ION
ratio instantly.
IOF F
1.5
Market Analysis
Undoubtedly, there is always got people one step ahead us. There is a
few simulators available in the market but not all of it are open source and free.
Hence, a good and free simulator is essential for the postgraduate researchers to
reduce the cost of research. Figure1.1 show the research and technology development
schedule proposed for carbon based nanoelectronic to impact industry’s timetable by
International Technology Roadmap for Semiconductor in 2009. From Figure 1.1,
carbon based devices still need a massive research to explore it capabilities to enter
industry production for coming years. Figure 1.2 is the percentage of the online user
against year for one of the simulation tools in the market. It showed the simulator
users are increasing gradually from years to years when carbon base device become
more and more vital for future electronic improvement.
4
Figure 1.1: Research and technology development schedule proposed for carbon based
nanoelectronic to impact industry’s timetable (Taken from ITRS 2009)
Figure 1.2: Percentage of simulation user for FETToy from 2003 until 2013 (Taken
from [1])
5
1.6
Contribution
Once ready, this simulator can be access for free and download by UTM
student. It can be used as standalone software without the installation of MATLAB so
that user can use it for their research or classroom teaching. Besides that, the simulator
also offer a simple way to generate voltage transfer characteristic (VTC) graph directly
from the I-V characteristic graph of PMOS and NMOS.
CHAPTER 2
LITERATURE REVIEW
2.1
The Fundamental of MOSFET
2.1.1
Basic of MOSFET
In 1959, John Atalla and Dawon Kahng at Bell Labs had successfully overcome
the problem of "surface states" that blocked electric fields from penetrating into the
semiconductor material and the first insulated-gate field-effect transistor (FET) was
invented. These "surface states" can be reduced at the interface between the silicon and
its oxide in a sandwich comprising layers of metal (M - gate), oxide (O - insulation),
and silicon (S – semiconductor). Hence, the name, ‘MOSFET’ is obtained [10]. After
years, MOSFET play an important role in computational and electronic field. The
MOSFET is used intensively and heavily in digital circuit applications and due to
its small sizes, millions of devices can be fabricated in a single integrated circuit.
Nowadays, MOSFET scaling has reach deep into sub 100nm barrier. MOSFET can
be categorized into two types, which are p-type and n-type MOSFETs or also known
as PMOS and NMOS respectively [4]. Electronic circuit design becomes versatile
and comprehensive when the two types of devices are used in the same circuit and
referred as complementary MOS (CMOS) circuits. Figure 2.1 shows the structure of
the MOSFET and Figure 2.2 shows the front view of the MOSFET.
7
Figure 2.1: The MOSFET structure (Taken from [2])
Figure 2.2: The front view MOSFET structure (Taken from [2])
2.1.2
Structure of MOSFET
MOSFET is a voltage-controlled power device and it has four terminals which
are drain (D), gate (G), source (S) and bulk (B) [4]. In general, there are two types
of MOSFET which is NMOS and PMOS. NMOS is a transistor with n+ in drain and
source regions embedded in p+ substrate where the current is carried by electrons flow
from drain to source. On the other hand, PMOS is a transistor with p+ in drain and
source regions embedded in n+ substrate where the current is carried by holes flow
from source to drain. The transistor level and front view of the PMOS and NMOS are
shown in Figure 2.3.
8
Figure 2.3: Transistor level and front view of the PMOS and NMOS (Taken from [3])
2.1.3
Operation of MOSFET
The heart of the MOSFET device is MOS capacitor. Basically, a capacitor
is formed when an insulator exist between the two voltage plate. In MOSFET, the
insulator is normally form by silicon oxide,SiO2 and the two voltage plate is the top
metal gate and semiconductor substrate. The following description is based on the
NMOS [4]. When a small gate voltage VG is applied (positive voltage at the gate
terminal while negative voltage at the source terminal), a depletion region is formed
due to the majority carriers (holes) in the p-type substrate are repelled with the positive
charge on the gate terminal. When the gate-source voltage (VGS ) is increasing, the
thickness of the depletion region is also increasing. This will cause the electric field
become stronger and start to attract the electrons. As VGS increases further, the number
of electrons under the depletion region is increased. This layer of electrons is called
an inversion layer. It will produce a channel between the source terminal and the drain
terminal which allow the current to flow through it. As long as the VGS is greater
than the threshold voltage, VT H , there is always a current flow through it. The same
principle is applied to the PMOS.
2.1.4
Liner mode
Linear mode will only occur when the gate-source voltage VGS is greater than
the threshold voltage (VT ) and small voltage (VDS ) is applied, a drain current (ID )
will flow between drain and source. A channel inversion charge will formed. Figure
2.4 shows the linear mode around the MOS capacitor. When drain voltage keep on
9
increasing till VDS >VGS -VT , the MOS capacitor will enter saturation mode instead of
linear mode.
Figure 2.4: Liner mode (Taken from [4])
2.1.5
Saturation Mode
When the gate-source voltage (VGS ) is increasing to point where its value same
with the value of gate-source voltage minus the threshold voltage, VDS ≥VGS -VT , the
channel at the drain terminal will reduced and become (pinch-off) and the channel
inversion charge become zero. The current condition of the MOSFET is in saturation
mode since the drain current (ID ) will remain constant. Figure 2.5 illustrates the
codition of the saturation mode of MOS capacitor.
10
Figure 2.5: Saturation mode (Taken from [4] )
2.1.6
Velocity Saturation
Velocity saturation occured when VDS > VDS (sat), the pinch-off point will
move closer to the source terminal. In this situation, electrons enter the channel at
the source, move along the channel toward the drain, then at the point where the
charge goes to zero, electric field force will pull the electron into the space charge
region. However, the electric field increase with gate voltage, the velocity of the carries
also increased. At higher field strength, the carriers fail to follow this principle. The
velocity of the carries tends to saturate due to the collision between the carries. This
phenomenon named as scattering effect.
11
Figure 2.6: Velocity Saturation (Taken from [4])
2.1.7
Limitation of Silicon Technology
According to Moore’s Law, the number of transistors that can be integrated
on a single die will be doubled in every two years [11]. A process called shrinking
has allowed this trend to be continued in these years. When the density of the silicon
transistor in an integrated chip increases to fulfil people’s demands. Many problems
will occur and inevitably it will reach its fundamental limitation of the silicon. Thus,
these limitations are bringing the life of silicon-based technology comes to the end.
Scaling down factor is the common way used by integrated chip manufacturer to
increase the functionality and performance. However, when the silicon technology
approach to Nano-level, the short channel effect is unavoidable. Function of transistor
in the integrated chip is act as a switch. When millions of the transistor in a single
chip function in a same time, the heat dissipation produced by them is uncontrollable.
Hence, the power consumption and the heat dissipation become major circumstances
in designing the silicon-made transistors. Speed and density of the complex chips
consume more power and at the same time dissipate more heat. The complexity of
the chips improves the chips’ performances as well as the cost of the production will
increase too. Therefore, there is a need of searching a new material to overcome the
limitations for silicon-based technology while CNT and GNR field-effect transistor
look promising for the future technology.
12
2.2
Graphene
Graphene was introduced to the world by the two physicist Andre Geim and
Novoselov in 2004. This material own a name of miracle material when it show
the unbelievable characteristic. Graphene is a flat monolayer of carbon atoms that
tightly packed into a two-dimensional (2D) honeycomb lattice. The greatness of
graphene is that it can forms into 3 carbon allotropes type: zero-dimensional (0D),
fullerenes/buckyballs, one dimensional (1D) carbon nanotube and three dimensional
(3D) graphite as shown in the Figure 2.7 [12].
Figure 2.7: Graphene able to construct three different carbon allotropes which are
buckyball, carbon nanotube and graphite(Taken from [5])
2.2.1
Graphene Nano Ribbon (GNR)
GNR or also known as nano-graphene ribbons are ultrathin oblong shape
obtained from graphene sheets which measured around nanometres in width. GNRs
were discovered by Mitsutaka Fujita and co-authors as theoretical model [13]. GNRs
are divided into two categories depending on the arrangement of the carbon atoms
which are armchair GNR (AGNR) and zigzag GNR (ZGNR). The differences between
these two GNR can be shown in Figure 2.8. By referring on Figure 2.8, armchair
13
cross-section on the edge in AGNR whereas ZGNR have zigzag cross-section on the
edge of the ribbons. Figure 2.8 also showed the calculation of armchair chain (Na) and
zigzag chain (Nz) in which the key point to determine the width of the ribbons.
Figure 2.8: Armchair and zigzag GNRs with lines N and width W (Taken from [6])
Figure 2.9: Proposed GNRFET structure
Graphene major drawback is that it is a zero bandgap material although it is
one of best alternative materials for nanoscale electronic applications and ballistic
electronics at room temperature. It causes the graphene to remain as metallic at charge
neutrality point which affects its usefulness in field-effect transistors. There is various
approaches which have been proven that graphene can open up its bandgap. One
14
of the approaches is partial hydrogenation of graphene towards fully hydrogenated.
Besides that, there is a direct approach in which the basal interaction of graphene with
substrate. Nevertheless, the bandgap produced by these techniques are so weak to gain
the substantial conductivity modulation. However, there is better approach to open
up the bandgap which is cutting the graphene sheet into stripes of GNRs. Figure 2.9
shows the structure of the graphene.
2.3
Carbon Nanotube (CNT)
A CNT can be considered as a graphene sheet that has been rolled up to form
a hollow cylinder [14]. Basically, there are two forms of CNT which are single-wall
carbon nanotubes (SWNT) and multi-wall carbon nanotubes (MWNT). The Figure
2.10 is SWNT and MWNT is as shown in Figure 2.11. Basically there are three types
of SWCNT: chiral CNT, armchair CNT and zigzag CNT. Figure 2.12 shows the three
types of CNT.
Figure 2.10: Single-wall carbon nanotubes (SWNT)
Figure 2.11: Multi-wall carbon nanotubes (MWNT) with three shells
15
Figure 2.12: The three configuration of CNT: (a) armchair (b) zigzag (c) chirality
2.3.1
Operation of CNTFET
The Schottky barrier CNTFET shown in Figure 2.13 works on the principle
of direct tunneling through the Schottky barrier and thermionic emission over the
barrier at the source-channel junction as shown in Figure 2.13. Electron tunneling
is the penetration of electrons through a potential barrier which they would not be
succeed to cross according to classical mechanics but still can be explained in quantum
mechanics. The barrier width is altered by the application of gate voltage. Therefore,
the transconductance of the device is rely on the gate voltage. The carrier transport
of a SB-CNTFET is via thermionic emissionand quantum tunneling at the conduction
and valence band resulting in a lower ON state current and limited conductance [6].
16
Figure 2.13: Schcottky barrier CNTFETs (Taken from [6])
2.4
Device Model
Basically, there is few types of device models for CNT and GNR FETs. The
most commonly use method are non-equilibrium Green’s function (NEGF) and topof-the-barrier method.
2.4.1
Non-equilibrium Green’s function (NEGF)
Non-equilibrium Green’s function is based on the transport theories which
developed by Lundstrom and Datta [15]. NEGF is the quantum transport device
modeling solution to the Schrödinger wave equation with open boundary conditions. It
is suitable for mesosopic device modeling as it is used based on bottom up simulation.
The Green’s function included Hamiltonian matrix (N ×N) based on a discrete lattice
with N grid points [16]. This calculation method is more precise as it will calculate
P P
P
each the N grid point of the lattice. Furthermore, self-energy matrices 1 , 2 and s
respectively as illustrated in Figure 2.4.1. It describes the influence of scattering into
the source and drain contact as well as scattering within the channel. Nevertheless, this
method will be complex to obtain a closed form of analytical model when the device
model consist huge N grid point. In addition, it will be costly in term of time and
money [6].
17
Figure 2.14: General matrix model for nanoscale device connected to two
contacts.(Taken from [6])
2.4.2
Top-of-the-barrier (TOB)
Top-of-the-barrier method is another alternative device modelling method. It is
a easier ballistic model that able to capture and solve the device physics efficiently
and effectively for analog or digital application. This method is originating from
the anylytical MATLAB script codenamed FETToy proposed by Rahman [1, 17] for
ballistic CNTFET transistor. Unlike Green’s function, TOB does not require every
single calculation for each lattice in the device to obtain the self-energy matrices. In
steady state, the number of carriers populating at the negative and positive velocity (or
momentum) vectors filled from the source and drain respectively are the same. Hence,
this will giving a zero drift velocity as demonstrated in Figure 2.4.2 [6].
18
Figure 2.15: Population of k-states at equilibrium at the top-of-the-barrier (Taken from
[6])
When an electric field (drain voltage applied) is applied across the channel from
the drain and source terminal, non-equilibrium mobile charge is be produced. Datta
introduced self-consistent voltage VSC formalism to calculate the voltage potential at
the top-of-the-barrier along the channel [18]. VSC is also known as the channel surface
potential. When gate and drain voltage is applied, the barrier voltage in the deviceis
pushed down and is described by VL . However, the charge brought by the additional
electron shifts the potential up by VP . A parasitic capacitance circuit model with
self consistent voltage at the top-of-the-barrier with grounded source and substrate
is illustrated in Figure 2.16 [6]. The carriers occupying the negative velocity k-states
are reduced by qVd when low drain bias is applied as illustrated in Figure 2.17. In large
drain bias, all the carriers will swift along the positive velocity k-states.
19
Figure 2.17: Population of k-states at non-equilibrium at the top-of-the-barrier (Taken
from [6])
Figure 2.16: A generic circuit model for ballistic transistor (Taken from [6])
20
Figure 2.18: Self consistent solution for USC and carrier density N (Taken from [6])
Therefore, top-of-the-barrier approach is much easier compare the NEGF method
The net current is given as the difference between the positive and negative
currents based on the Landauer-Buttiker formalism is show in the equation 2.1. [19].
Ids = GON
Ids (VG , Vd , VS )
GON
=
GON
USF
UDF
KB T
[=0 (
) − =0 (
)]
q
KB T
KB T
(2.1)
q(EF − VSC (VG , Vd , VS ))
KB T
[log(1 + exp(
)]−
q
KB T
KB T
q(EF − VSC (VG , Vd , VS ) − Vd − VS )
[log(1 + exp(
)]
q
KB T
(2.2)
Equation 2.1 can be rewritten as 2.2 in the function of the drain voltage, source
voltage and gate voltage coefficient [6] where GON is the ON-conductance and =0 is the
Fermi-Dirac integral function [20, 21]. The quantum conductance limit of a ballistic
2
2
SWCNT and GNR is GON = 4qh and GON = 42q
respectively [22].
h
The drain current, Ids computation requires self consistent solution shown
in Figure 2.18. Initially, a random value of N is assigned to yield an arbitrary
potential called USC . A converged N and USC will be reached when few iterations
are performed. Consequently, we can calculate the injected current from the source
and drain ( I + and I − ) for a fixed gate and drain voltage bias.
21
Figure 2.19: The layout of the CNT simulator of NEMO-VN1 (Taken from [7])
2.5
Existing Simulator
There is a few simulation tools that available in the market such as FETToy,
NEMO-VN1 and Quantum Wise. These simulation tools allow the users to insert their
desired parameters to observe the simulation result and on spot analysis.
2.5.1
NEMO-VN1
NEMO-VN1 is a quantum simulator released in 2009 by a group of Vietnamese
researchers. This simulator is using non-equilibrium Green’s function for all the
simulation. Besides that, this simulator did not include GNR which is the limitless
for those research works on the carbon based devices. In addition, this simulator
has limited functionality that restrict the user to calculate the essential electrical
characteristic of the device as shown in Figure below. This simulator is not a free
and open source software and hence difficult to access [7].
22
Figure 2.20: Atomistix ToolKit(ATK) (Taken from [8] )
2.5.2
Quantum Wise
Quantum Wise is a well known software company for producing simulation
tools. Its commercialize software product Atomistix ToolKit (ATK) consist of a
lot of functionality either in atomic-scale modelling and electronic characteristic
computational. It used non-equilibrium Green’s function method for the CNT and
GNR simulation. Besides that, it has a nice graphical user interface for the simulation
users which is user friendly and attractive. Nevertheless, this simulator is very
expensive as its was commercialise products with multi functionalities [8].
2.5.3
Purdue Nano-hub (FETToy)
FETToy is a simulation tools launch by few scientists from different
universities. FETToy actually is the free online simulation tools but it require an user
id for log in prupose. This simulator using the top-of-the-barrier approach instead
of NEGF method. Although it has nice graphical user interface, the functionality of
FETToy is still restricited to a few devices such carbon nanotube, silicon nanowire
MOSFET and double gate MOSFET [1].
23
Figure 2.21: FETToy simulator layout for Silicon Nanowire MOSFET (Taken from
[1])
CHAPTER 3
RESEARCH METHODOLOGY
3.1
Introduction
This project is mainly create a simlation tools for the carbon based devices
GNR and CNT FETs to allow the users to bench mark and on spot analyse the
simulation result. This project will combine all the MATLAB script code from
previous findings of Tan [6] and compromise together in the MATLAB GUI. Besides
that, the simulator will work in a standalone software and include some features for
users to trade off between speed and accuracy. Consequently, the research of this
project are shown as below:
1.
Literature review of journals, books, internet and conference papers on GNR and
CNT characteristics.
2.
Research on the simulation tools available in the market and their pros and cons.
3.
Understand the matlab code by previos finding and combine them in MATLAB
GUI.
4.
A comprehensive graphical user interface will designed for the simulator and
new algorithm to auto generate VTC graph was created.
5.
Testing the accuracy of the simulation result and working on standalone
availability.
25
28
3.2
Methology Work Flow
3.1 Methology Work Flow
This project follows the work flow as design at Figure 3.1.
Literature review
Understand the
characteristic for
carbon base device
Create the algorithm
in m-script file for
device simulation
Master the
MATLAB GUI
concept
Design the interface
layout for the
simulator
Executing the
simulator as a
standalone software
Figure 3.1: The flow chart of the project
26
3.3
Device Modeling
This simulation tools will using the top-of-the-barrier approach method for
GNR and CNT. The complexity of this method is less compare to the non-equilibirum
Green’s function. This model is a simpler ballistic approach compare to NEGF
modeling.
3.4
MATLAB
MATLAB is calculation software used to solve complex equations, data
analysis and comparing the developed model with published models for this project.
Moreover, it is interactive and integrated environment software as well for symbolic
computation, numerical computations and scientific visualization. This software was
created by a numerical analyst, Cleve Moler of the Mathworks, thus, it operates for
Matrix Laboratory in 1970. MATLAB is popular and welcome by most researcher
because it is able to simplify tedious works related with solving problem numerically.
MATLAB contributes convenient way for its user to deliberate and analyze frequently.
This means that its program operates in interpreted and respected algorithm. Besides
that, this software use automotive memory management which is more convenient as
it does not require any array declaration. Below is the list of other advantages:
•
It has powerful operation in which utilizes only one or two commands.
•
It has own set of function for certain applications which can be developed.
•
It has best graphic facilities to view.
3.4.1
MATLAB GUIDE
A graphical user interface (GUI) is a graphical display in one or more windows
containing controls, called components, that enable a user to perform interactive tasks.
The user of the GUI does not have to create a script or type commands at the command
line to accomplish the tasks. Unlike coding programs to accomplish tasks, the user of
a GUI need not understand the details of how the tasks are performed.
27
MATLAB Graphical User Interface Deveplopment Environment (GUIDE) is
the GUI software that provided with MATLAB application. It is used to design the
for this simulation tools because it is object oriented programming software. Object
oriented softare will auto generate a MATLAB code for controlling the way the GUI
works. Therefore, it is easier and faster for programmers to create a nice interface.
Besides that, GUIs created by using MATLAB GUIDE can also perform any type of
computation, read and write data files, communicate with other GUIs, and display data
as tables or as plots. This will allow programmer to design their simulation flow with
existing script file. In addition, MathWorks Inc released MATLAB GUI user guide for
novice programmer to study the function of it [23].
CHAPTER 4
RESULT AND DISCUSSION
4.1
Introduction
A new simulation tool, LODISI (LOw DImensional SImulator) was
successfully created by using MATLAB GUIDE. MATLAB GUIDE is the software
used to design the interface of the LODISI. The device modelling of this simulator
is based on top-of-the-barrier method which is originated from the framework of
the FETToy of the Purdue Univeristy. LODISI is comprehensive and user friendly
graphical user interface with its editable input parameters, ajustable sliders and plenty
type of graphs provided for analysis.
4.2
LODISI
LODISI offers two different types of simulation for the users to access,
carbon nanotube (CNT) and graphene nanoribbon (GNR). LODISI for both type of
simulations can be accessed by a main user’s interface. The main user’s interface is a
graphical user interface that allow users to choose the desired simulation by clicking
the repective buttons. To increase the accessibility of this simulator, both LODISI are
design to work simutaneously at the same time. The main interface for the LODISI
showed in below Figure 4.1. Users are given the options to choose between CNT and
GNR by clicking the button in the window respectively as illustrated in Figure 4.1.
29
Figure 4.1: The main interface of LODISI
The atomic sturcture for CNT and GNR also included and place above their
buttons in order to help users in choosing the simulation types. Once the button of
CNT is pressed, a new simulator window for CNT will popup automatically as shown
in Figure 4.2, and the same goes to the GNR as shown in Figure 4.3.
30
Figure 4.2: The interface for the LODISI CNT
Figure 4.3: The simulator window for LODISI GNR
The difference between the LODISI GNR and LODISI CNT is their input
parameter. LODISI CNT need diameter value for the simulation as CNT is a hollow
tube field-effect transistor. While LODISI GNR need the chirality number to determine
the width of the graphen nanoribbon instead of diameter as its not a tube shape channel
length. The input parameters for CNT and GNR are shown in the Table 4.1.
31
Table 4.1: The input parameter and default value for the LODISI CNT and LODISI
GNR
Parameter
Symbol
EF
Fermi Energy (Source)
Gate control
alphag
Drain control
alphad
Gate insulator thickness
Gate Oxide thickness (m)
Gate insulator dielectric constant
epsr
Diameter (CNT only)
diameter
Chirality (GNR only)
chirality
Temperature
temperature
No of bias point
NV
Initial voltage
VI
Final voltage
VF
4.2.1
Default Value Default Value
CNT
GNR
n-type p-type n-type p-type
-0.32
0.32
-0.22
0.22
0.88
0.88
0.032
0.035
-8
-9
1.0 × 10
25
-9
1.5437 × 10
300
20
0
1
-1
2.0 × 10
25
19
300
20
0
1
-1
LODISI Function Button
A few buttons added into the user interface to increase the functionality of
LODISI:
•
Default button
A default button is set in both LODISI to automatic insert the default parameters into
the simulator that preset in the algorithm. This button function aim to reduce the
burden of changing input parameters repeatedly when benchmarking projects. The
default value for each parameter for CNT and GNR are show in the Table 4.1.
•
Reset button
Reset button is a inevitably button that needed for every simulation tools. Reset button
will reset all the input parameters that allow users to restart a new simulation.
•
Run button
Run button is the most important button in LODISI. Run button must be pressed every
time in order to get the simulation result after insert all the input parameters. After the
32
run button was click, the value for DIBL and SS will be calculated automatically and
displayed at the bottom part of the axes.
•
VTC button
This button is the unique button for the LODISI. Whenever this button is pressed, it
will automatically display the voltage transfer characteristic (VTC) graph in the axes.
At the same time, the gain for the CMOS inverter will be calculated and show at the
GAIN editbox.
•
Close button
Close button is the normally seen button that will quits the simulation of LODISI but
will not close the main interface of the LODISI.
4.2.2
Graph Option and Metric Performance
LODISI provides few graph options and metric performance for users to
study the electrical characteristic of CNT and GNR. The option of graphs include
I-V characteristic graph, NMOS-PMOS field-effect transistor (NP-FET) and Voltage
transfer characteristic graph (VTC). These graphs will be display at the axes area as
users choose the options in the n-type and p-type popup menu bar. LODISI only allow
users to choose one type of graph to display after user make their choice. The graph
types that included in LODISI shows at the Table 4.2. The important I-V characteristic
graphs is drain current versus drain voltage graph and drain current versus gate voltage
graph. Based on the I-V characteristic graphs, the performance of a transistor could be
easily predict and conclude. In addition, the meteric parameter such as DIBL and SS
can be analyzed through these graph. Others than the I-V characteristic graph, LODISI
also include quantum physic graph such as mobile charge against gate voltage graph,
average velocity against gate voltage graph, mobile charge against drain voltage graph
and quantum capacitance against gate voltage graph.
33
Table 4.2: List of plot options and metric performance of LODISI
Type of Graph
Drain Current vs Drain voltage
Drain Current vs Gate voltage
Drain Current vs Gate voltage(semilog)
Mobile Charge vs Gate voltage
Average velocity vs Gate voltage
Mobile Charge vs Drain voltage(semilog)
Mobile charge vs Drain voltage
Quantum Capacitance vs Gate voltage
NP-FET
List of Metric Performance
DIBL
SS
GAIN
4.2.2.1 Drain Current versus Drain Voltage Characteristic
The relationship of the drain current of a ballistic carbon nanostructure is vital
to measure the drive strength of a transistor for a higher or reduced performance. The
drain current as a function of drain voltage (I-V) for a wide range of gate voltage for
n-type CNTFET is shown in Figure 4.4, for p-type in Figure 4.5. From the plot, the
drain current increase gradually with drain voltage and remain constant after reach
saturation. Hence, we can obtain the saturation drain voltage VDSAT that cause the
saturation current at different gate voltage. VDSAT is important metric performance in
CMOS analog design.
34
7
x 10
-5
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
6
Drain Current IDS (A)
5
4
3
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
0.0526
0.105
0.158
0.211
0.263
0.316
0.368
0.421
0.474
0.526
0.579
0.632
0.684
0.737
0.789
0.842
0.895
0.947
1
2
1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Drain Voltage VD (V)
0.7
0.8
0.9
1
Figure 4.4: Drain current versus drain voltage of a n-type CNTFET using the default
parameter in tabulated in Table 4.1
35
x 10
7
-5
6
4
3
2
| Drain Current IDS (A) |
5
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
-0.0526
-0.105
-0.158
-0.211
-0.263
-0.316
-0.368
-0.421
-0.474
-0.526
-0.579
-0.632
-0.684
-0.737
-0.789
-0.842
-0.895
-0.947
-1
1
-1
-0.8
-0.6
-0.4
Drain Voltage VD (V)
-0.2
0
0
Figure 4.5: Drain current versus drain voltage of a p-type CNTFET using the default
parameter in tabulated in Table 4.1
4.2.2.2 Drain Current versus Gate Voltage Characteristic
Drain current versus gate voltage for n-type GNRFET depicted in Figure 4.6
and Figure 4.7 are another important plot for further analysis of a nanotransistor. It
provides the value of threshold voltage point for the transistor to turn on at different
drain voltages. From the drain current against gate voltage graph, the current on/off
ON
ratio) and SS can be calculated. Semilog graph of drain current versus gate
( IIOF
F
ON
voltage are to ease the calculation of IIOF
ratio by deduct the highest current to the
F
lowest current. Subthreshold swing can be obtain by calculating the reciprocal of the
slope of the drain current versus gate voltage. The metric performance is vital to design
a good transistor.
36
2.5
x 10
-5
VDs=0.0909
VDs=1
Drain Current IDS (A)
2
1.5
1
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.6: Drain current versus gate voltage for n-type GNRFET with default
parameters
-4
10
VDs=0.0909
VDs=1
-5
10
-6
Drain Current IDS (A)
10
-7
10
-8
10
-9
10
-10
10
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.7: Semilog plot of drain current, IDS against gate voltage, VG for the default
parameters of n-type GNRFET
37
4.2.2.3 Mobile Charge versus Gate Voltage Graph
In microelectronic, when the gate voltage increase it will cause some effect to
the electron mobility in the channel length. This graph mean to study the relationship
between the electron mobility and the gate voltage. Figure 4.8 illustrated the plot of
mobile charge against gate voltage for n-type CNTFET.
16
x 10
-11
VDs=0.0526
VDs=1
14
12
Mobile Charge (C/m)
10
8
6
4
2
0
-2
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Votlage VG (V)
0.7
0.8
0.9
1
Figure 4.8: Mobile charge versus gate voltage for the n-type CNTFET with default
parameters
4.2.2.4 Average Velocity versus Gate Voltage Graph
Average electron velocity against gate voltage is another graph study of the
ballistic transistor on the movement of the electron. Since, the carbon based device
transistor are ballistic transistor, the average velocity of the transistor will increase
when the gate voltage increase as the electron gain more energy and move faster. The
plot of average electron velocity against gate voltage as shown at Figure 4.9.
38
6.5
x 10
5
6
5.5
Average Velocity (m/s)
5
4.5
4
3.5
3
2.5
2
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.9: Average velocity versus gate voltage for the n-type CNTFET with default
parameters
4.2.2.5 Mobile Charge versus Drain Voltage Graph
Figure 4.10 shows the relationship between the drain voltage and the mobile
charge. The mobile charge of the transistor all to a constant value at a certain value for
every gate voltages.
39
16
x 10
-11
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
Vgs
14
12
Mobile Charge (C/m)
10
8
6
4
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0
0.0526
0.105
0.158
0.211
0.263
0.316
0.368
0.421
0.474
0.526
0.579
0.632
0.684
0.737
0.789
0.842
0.895
0.947
1
2
0
-2
0
0.1
0.2
0.3
0.4
0.5
0.6
Drain Voltage VD (V)
0.7
0.8
0.9
1
Figure 4.10: Mobile charge versus drain voltage for the n-type CNTFET with default
parameters
4.2.2.6 Quantum Capacitance versus Gate voltage Graph
Figure 4.11 depicts relationship between the quantum capacitance and gate
voltage in the CNT/GNR FET. When the gate voltage increase, the electric field will
increase, the parasitic capacitance of the transistor will increase as well.
40
6
x 10
-10
Quantum Capacitance (F/m)
5
4
3
2
1
VDs=0.0526
VDs=1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.11: Quantum capacitance versus gate voltage for the n-type CNTFET with
default parameters
4.2.2.7 Nmos-Pmos Field-effect Transistor Plot (NP-FET)
NP-FET graph is one of the special features of the LODISI. NP-FET will shows
drain characteristics by two different types of CNT or GNR plot simultaneously. The
graph is plotted by inverting the PMOS graph result in a mirror image of the drain
characteristics. An algorithm created to detect the interception point of n-type and
p-type for each gate voltage. The algorithm is modify based on the exchange file
named “interception” by Douglas M. Schwarz [24]. The interception point will be
marked as the red dashed line. In Figure 4.12, the red dashed line represents the CMOS
voltage transfer characteristic (VTC) for different gate voltages. This curve is then
reused to plot the voltage transfer characteristics curve. In order to generate this graph,
the number of bias points must be equal for both transistors. The NP-FET graph for
GNRFET is shown in Figure 4.13.
41
Figure 4.12: I-V characteristics for n-type (green line) and p-type (blue line) CNTFET
for VG = 0 V to 1 V (bottom up) in 0.0526 V spacing. The red dashed line represents
the drain current in the CNT-based CMOS inverter
42
Figure 4.13: I-V characteristics for n-type (green line) and p-type (blue line) GNRFET
for VG = 0 V to 1 V (bottom up) in 0.0909 V spacing. The red dashed line represents
the drain current in the GNR-based CMOS inverter
4.2.2.8 Voltage Transfer Characteristic (VTC)
•
Default value
The voltage transfer characteristic graph will be automatically generated when the
VTC button is pressed. The data is retrieved from the red dashed line in the NPFET graph. A new source code created to re-plot the red dashed line by changing the
x-axis to its gate voltage values and the y-axis to its drain voltage values. From the
VTC curve, gain is calculated by the gradient of the steepest slope of the curve. Figure
4.14 show the VTC graph for the default value for CNTFET.
43
1
0.9
0.8
Drain Voltage VD (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.14: Voltage transfer characteristic for an almost symmetrical I-V for n-type
and p-type CNTFET with source fermi energy, EF = -0.32 eV (n-type) and 0.32 eV
(p-type)
•
Different values of source fermi level energy
LODISI also accept the simulation of CMOS-like CNT with different source Fermi
energy for n-type and p-type CNTFET as shown in Figure 4.15. Compared to Figure
4.14, the VTC gradient is shifted toward the left of the x-axis, implying an earlier
saturation of p-type CNT and a much higher mobility for n-type CNT.
44
1
0.9
0.8
Drain Voltage VD (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Gate Voltage VG (V)
0.7
0.8
0.9
1
Figure 4.15: The VTC graph of asymmetrical I-V for n-type CNTFET with EF =-0.32
eV and p-type CNTFET with EF =0.64 eV PMOS
4.2.3
LODISI GNR
LODISI-GNR is a bit different than LODISI-CNT although the source code
is almost the same for both of them. Basically, both LODISI are using the top-ofthe-barrier approach. The different between them was the GNRFET requires chirality
number in the drain current calculation instead of diameter. According to their findings
[25, 26], the energy dispersion in GNR is depending on the chirality number. With
different chirality number, the GNR will induced different energy dispersion will cause
it in semiconductor or metallic. Based on the CNT and GNR bandgap calculation
Table [6], an algorithm created to differentiate the type of GNR with different chirality
number. LODISI-GNR will include a warning panel at the left top of the LODISI’s
interface. LODISI will remind the users when they insert wrong chirality number that
will induce a metallic GNRFET as shown at Figure 4.16. Besides, LODISI will not
functioning when wrong chirality number is inserted.
45
Figure 4.16: “Wrong Chirality number. Now it is metallic” will be shown in the
warning panel when the wrong chirality number inserted
4.2.4
Standalone Software
LODISI successfully changed to a window standalone application which do
not require the users to install MATLAB for it. This is done by using the deploytool
function in MATLAB. Deploytool function will include all the MATLAB m script
file to a single EXE file as show at Figure 4.17. However, users need to install the
MATLAB Compiler Runtime (RMC) file for it to run succesfully. Because lot of the
MATLAB m scirpt file in LODISI, LODISI standalone application require 437MB.
The size of the application can be reduced in future by restructure the LODISI’s m
script file. Since the size of this application is big, it need few minutes for the LODISI
interface to popup after double click it.
Figure 4.17: LODISI window standalone application
CHAPTER 5
PROJECT MANAGEMENT
5.1
Introduction
A good project management is the key to success a project efficiently and
effectively. The objective of project management is to achieve all project goals with
effective project planning, organizing, and controlling resource within a specified
time period. The primary constraints in this project are the research scope, research
time, research budget and human resource to perform the required activity. Gantt
chart is the tabulated project schedule which become the guideline to accomplish
this project by time. In addition, cost estimation on the components is taking into
consideration to ensure minimal project cost while keeping project to achieve the
required requirement. Therefore, project management is essential for every project
in order to reduce unnecessary time and money.
5.2
Project Schedule
Table 5.1 shows project Gantt chart of semester one. From Table 5.1 shows
that there is a delay in the commencement of the research work due to the late final
year project seminar. At the meantime, student also took longer time when choosing
their respective research topic and scope. After project title selection and submission,
literature review is carried out. Nevertheless, the actual planning took more time than
originally planned considering the new findings in microelectronics. Learning to use
MATLAB is also time consuming as the author did not have any knowledge of basic
MATLAB programming and GUI.
47
Table 5.1: Project Gantt Chart (Semester One)
Sep-13
1
2
Oct-13
3
4
5
6
Nov-13
7
8
9
Project Proposal
Planned
Actual
Literature Review
10
Dec-13
11
12
13
14
15
16
Semester Break
Month
Week
Activities
Project Course Background
Study
Determine the title of the
project
MATLAB Learning Courses
Preparation for Presention
FYP1
FYP1 Report Writing
Table 5.2 shows the project Gantt chart of semester two. In contrast to Gantt
chart semester one, Gantt chart in second semester shows an unexpected long delay
in some task at end of the project schedule. The delay in designing graphical user
interface is MATLAB GUIDE does not consist tab-function. Hence, time used up to
find an alternative way to create tab function in the graphical user interface. Because
of this, other task such as create the m-script code for VTC and standalone application
are postponed.
Table 5.2: Project Gantt Chart (Semester Two)
Month
Week
Activities
Feb-14
1
2
3
Mar-14
4
5
6
7
PLANNED
ACTUAL
Apr-14
8
9
10
Short Sem Break
Thesis writing
19 - - -
Break
ECEX Exhibition preparation
18
Semester
Learning the MATLAB GUIDE
Designing the graphical user
interface
Create the m-script code and
standalone application
Final checking on the
simulation result
Jan-14
17
11
May-13
12
13
14
15
16
48
5.3
Cost Estimation
This project is cost effective because it is software based and no expenditure
is required. The MATLAB software is free which can be downloaded UTM website.
Therefore, this project does not require any cost. In future, there may be additional
cost incurred for the commercialization of LODISI as a quantum-one-dimensional
software. Some MATLAB courses need to attend to increase the functionality of the
LODISI.
CHAPTER 6
CONCLUSION
The time for carbon based device transistor is around the corner when
silicon based transistor has reach its’ limit. Undoubtedly, LODISI will be one
of the comprehensive software that prepare the ground for the development of the
electronic technology. Based on the modelling framework of top-of-the-barrier
approach, LODISI were successfully created by using MATLAB GUIDE with
attractive interfaces. From result and discussion, LODISI show the ability to predict
and display the correct electrical characteristic for both type of transistors. LODISI is
different than others software is it has various functionalities as it included both type
of carbon based devices. Besides that, the main differences between LODISI and other
simulations tools are that LODISI includes unique features such as a VTC graph, autocalculating DIBL, SS and Gain. Hence, LODISI become a better platform for users to
benchmark their project and design verification.
6.1
Future Work
Future work for this project is to improve the functionality of the LODISI
to include non-idealities cases such as phonon scattering and benchmarking against
Predictive Technology Model (PTM) of short channel MOSFET of various technology.
Furthermore, LODISI can be add in some plugin to make it more portable and attractive
interface. This can be done by transplant the MATLAB algorithm to different software
such as Microsoft Visual Studio. The algorithm of the LODISI can be improved further
by shorten and restructure the m script file which will result a small size application.
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APPENDIX A
NP-FET
Coding in the matlab m-script
Ipn= f l i p l r ( Ip ) ;
Ipn_n= f l i p u d ( Ipn ) ;
h1= p l o t ( h a n d l e s . a x e s 1 , V, I , ’ − g ’ , V, Ipn_n , ’ − b ’ ) ;
string_matrix =[];
f o r m= 1 :NV
string_matrix =
s t r v c a t ( s t r i n g _ m a t r i x , [ ’ Vgs = ’ , n u m 2 s t r (V(m ) , 3 ) ] ) ;
end
f o r kVg = 1 :NV
[A ( : , kVg ) , B ( : , kVg ) ] =
i n t e r s e c t i o n s (V, I ( : , kVg ) , V, I p n _ n ( : , kVg ) ) ;
end
h o l d on ;
h1= p l o t ( h a n d l e s . a x e s 1 , A, B,’−− r ’ , ’ L i n e w i d t h ’ , 3 . 0 ) ;
hold off ;
x l a b e l ( ’V_D [ V o l t ] ’ ) ;
y l a b e l ( ’ I _ {DS} [A ] ’ ) ;
t i t l e ( ’ Graph o f I _ {DS} v e r s u s V_D f o r N−t y p e and P−t y p e ’ ) ;
APPENDIX B
VTC
Coding in the matlab m-script
Ipn= f l i p l r ( Ip ) ;
Ipn_n= f l i p u d ( Ipn ) ;
f o r kVg = 1 :NV
[A ( : , kVg ) , B ( : , kVg ) ] =
i n t e r s e c t i o n s (V, I ( : , kVg ) , V, I p n _ n ( : , kVg ) ) ;
end
d o u b l e tem2 ;
VA= l i n s p a c e ( 0 , 1 ,NV) ;
h1= p l o t ( h a n d l e s . a x e s 1 , VA, A , ’ − r ’ ) ;
m i d d l e = r o u n d (NV / 2 ) ;
g e t x = [ VA( m i d d l e ) VA( m i d d l e + 1 ) ] ;
g e t y = [ A( m i d d l e ) A( m i d d l e + 1 ) ] ;
GAIN = p o l y f i t ( g e t x , g e t y , 1 ) ; % Gain i n t h e f i r s t number
g a i n = GAIN ;
set ( handles . edit28 , ’ String ’ , gain ( : , 1 ) ) ;
xlim ( [ 0 , 1 ] ) ;
ylim ( [ − 0 . 0 5 , 1 . 0 5 ] ) ;
x l a b e l ( ’V_G [ V o l t ] ’ ) ;
y l a b e l ( ’V_D [ V o l t ] ’ ) ;
t i t l e ( ’ Graph o f V_D v e r s u s V_G ’ ) ;

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