NAME SURNAME:
NUMBER:
CEN 425 Embedded Systems
STM32F429 Discovery Board System Clock
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock
HSE oscillator clock
Main PLL (PLL) clock
The devices have the two following secondary clock sources:
32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the
RTC used for Auto-wakeup from the Stop/Standby mode.
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC clock (RTCCLK).
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
PLL_M 0 - 63 (1 – 2 MHz),
PLL_N 192 - 432 (192 – 432 MHz),
PLL_P {2, 4, 6, 8} (not exceed 168 MHz),
PLL_Q 4 – 15.
It's a must initialize the structure that refer the peripherals that you need to use, for do this are necessary two
steps:
1) Declare the appropriate variable.
/* Private variables */
GPIO_InitTypeDef GPIO_InitStructure;
RCC_ClocksTypeDef RCC_ClockFreq;
2) Initialize the peripheral structure. Below there is the I/O and SPI example.
/* Configure Leds (PC8 & PC9) mounted on STM32 Discovery board - OutPut Push Pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
Add the appropriate peripheral driver file into: StdPeriph_Driver.
Figure 1. Clock tree
RCC_ClocksTypeDef Struct
(220/1713 Doc ID018909 Rev 7)
RCC clock control register (RCC_CR)
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
/* Reset the RCC clock configuration to the default reset
Set by hardware to indicate that PLL is locked.
state ----*/
0: PLL unlocked
/* Set HSION bit */
1: PLL locked
RCC->CR |= (uint32_t)0x00000001;
2
void RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
Note: The default reset state of the clock configuration is given below:
HSI ON and used as system clock source.
HSE, PLL and PLLI2S OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS, MCO1 and MCO2 OFF
All interrupts disabled
This function doesn't modify the configuration of the
Peripheral clocks
LSI, LSE and RTC clocks
Parameters: None.
Return values: None.
void RCC_HSEConfig (uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Note: After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag
to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock. HSE state can not be
changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the
system clock then change the HSE state (ex. disable it). The HSE is stopped by hardware when entering STOP and
STANDBY modes. This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you
have to enable it again after calling this function.
Parameters:
RCC_HSE: Specifies the new state of the HSE. This parameter can be one of the following values:
RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
RCC_HSE_ON: turn ON the HSE oscillator.
RCC_HSE_Bypass: HSE oscillator bypassed with external clock.
Return values: None.
void RCC_GetClocksFreq (RCC_ClocksTypeDef* RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Note: The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the
predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE.
If SYSCLK source is HSE, function returns values based on HSE_VALUE.
If SYSCLK source is PLL, function returns values based on HSE_VALUE or HSI_VALUE multiplied/divided by the
PLL factors.
Parameters:
RCC_Clocks: Pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note: This function can be used by the user application to compute the baudrate for the communication peripherals or
configure other parameters. Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to
update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values: None.
3
void RCC_PLLConfig (uint32_t
uint32_t
RCC_PLLSource, uint32_t
PLLM, uint32_t
PLLN,
PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
Note: This function must be used only when the main PLL is disabled.
Parameters:
RCC_PLLSource: Specifies the PLL entry clock source. This parameter can be one of the following values:
o
RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry.
o
RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry.
Note: This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Parameters:
PLLM: specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.
Note: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is
recommended to select a frequency of 2 MHz to limit PLL jitter.
Parameters:
PLLN: specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192
and 432.
Note: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
Parameters:
PLLP: specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range
{2, 4, 6, or 8}.
Note: You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.
Parameters:
PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between
4 and 15.
Note: If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock
for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Return values: None.
void RCC_PLLCmd (FunctionalState NewState)
Enables or disables the main PLL.
Note: After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock
is stable and can be used as system clock source. The main PLL can not be disabled if it is used as system clock source.
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters:
NewState: New state of the main PLL. This parameter can be: ENABLE or DISABLE.
Return values: None.
4
uint32_t SysTick_Config (uint32_t ticks)
Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the
specified time interval. Counter is in free running mode to generate periodical interrupts.
Parameters:
[in] ticks Number of ticks between two interrupts
Returns:
0 - success
1 - failure
Note: When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the
file device.h must contain a vendor specific implementation of this function.
void SysTick_Handler (void)
This function handles SysTick Handler.
Parameters: None.
Return values: None.
void Delay (uint32_t nTime)
Inserts a delay time.
Parameters:
nTime: specifies the delay time length, in milliseconds
Return values: None .
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Note: Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed
the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration
functions").
Parameters:
RCC_SYSCLK: defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter
can be one of the following values:
o
RCC_SYSCLK_Div1: AHB clock = SYSCLK
o
RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
o
RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
o
RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
o
RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
o
RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
o
RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
o
RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
o
RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values: None.
5
void RCC_PCLK1Config (uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Parameters:
RCC_HCLK: defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be
one of the following values:
o
RCC_HCLK_Div1: APB1 clock = HCLK
o
RCC_HCLK_Div2: APB1 clock = HCLK/2
o
RCC_HCLK_Div4: APB1 clock = HCLK/4
o
RCC_HCLK_Div8: APB1 clock = HCLK/8
o
RCC_HCLK_Div16: APB1 clock = HCLK/16.
Return values: None.
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Note: The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and
STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System
CSS is enabled). A switch from one clock source to another occurs only if the target clock source is ready (clock stable after
startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source
will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock
source.
Parameters:
RCC_SYSCLKSource: Specifies the clock source used as system clock. This parameter can be one of the following
values:
o
RCC_SYSCLKSource_HSI: HSI selected as system clock source
o
RCC_SYSCLKSource_HSE: HSE selected as system clock source
o
RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values: None.
Laboratory Task:
Write the required C program code that lits the LEDs on STM32F429ZI Discovery Board,
sequentially.
The Green user led on the STM32F429ZI Disco Board is ON firstly with a defined period of time.
Then the other led is ON with another defined period of time by system clock.
After debugging the code sequence, at the debug session observe the clock registers and note all
the values at the given table. Also, measure the output signal period (led period) by oscilloscope.
Note here your observations after conducting the experiment.
o
Explain the behaivor of the board.
o
Calculate the expected output (LED) period by the given equation on the first page. After
that calculation measure this period by using oscilloscope. Use the GND and PG13 pins
on the Disco Board. Compare these two values. If is there any difference between these
values, explain why.
o
Change the PLL paramaters the given values then calculate the periods for both the leds
and repeat the procedure.
o
Change the numbers in the “SysTick_Config” and “Delay” functions. Observe the
operation of the board and note the changes.
6
#include "stm32f4xx.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_rcc.h"
uint32_t TimingDelay;
uint32_t count = 10;
void Delay(uint32_t nTime);
void Mode1(void);
void Mode2(void);
void RCC_WaitForPLLStartUp(void) {
while ( (RCC->CR & RCC_CR_PLLRDY) == 0 ) {
__NOP();
}
}
int main(){
GPIO_InitTypeDef GPIO_InitDef;
RCC_ClocksTypeDef RCC_ClockFreq;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);
GPIO_InitDef.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14;
GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
//Initialize pins
GPIO_Init(GPIOG, &GPIO_InitDef);
while(1) {
if (count == 10){
while (count > 0){
Mode1();
RCC_GetClocksFreq(&RCC_ClockFreq);
SysTick_Config(4000);
GPIO_SetBits(GPIOG, GPIO_Pin_13);
Delay(1000);
GPIO_ResetBits(GPIOG, GPIO_Pin_13);
Delay(1000);
count--;
}
}
if (count == 0){
while (count < 11){
Mode2();
RCC_GetClocksFreq(&RCC_ClockFreq);
SysTick_Config(4000);
7
GPIO_SetBits(GPIOG, GPIO_Pin_14);
Delay(1000);
GPIO_ResetBits(GPIOG, GPIO_Pin_14);
Delay(1000);
count++;
}
count = 10;
}
}
}
void Delay(uint32_t nTime){
TimingDelay = nTime;
while(TimingDelay != 0);
}
void SysTick_Handler(void){
if (TimingDelay != 0){
TimingDelay--;
}
}
void Mode1() {
RCC_DeInit();
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == ERROR) {
return;
}
RCC_PLLConfig(RCC_PLLSource_HSE, 48, 192, 8, 15);
RCC_PLLCmd(ENABLE);
RCC_WaitForPLLStartUp();
RCC_HCLKConfig(RCC_SYSCLK_Div4);
RCC_PCLK1Config(RCC_HCLK_Div16);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
}
void Mode2() {
RCC_DeInit();
RCC_HSEConfig(RCC_HSE_ON);
if (RCC_WaitForHSEStartUp() == ERROR) {
return;
}
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 15);
RCC_PLLCmd(ENABLE);
RCC_WaitForPLLStartUp();
RCC_HCLKConfig(RCC_SYSCLK_Div4);
RCC_PCLK1Config(RCC_HCLK_Div16);
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
}
8
Table 1. Frequency (Period) Measurements
SYSCLK_
HCLK_
PCLK1_
PCLK2_
Measured LED
Calculated
Frequency
Frequency
Frequency
Frequency
(PG13) Period
Period
Step 1.
Green Led
Red Led
Step 2.
Mode 1
PLLM = 24
PLLN = 192
PLLP = 2
PLLQ = 15
Mode 2
PLLM = 16
PLLN = 336
PLLP = 4
PLLQ = 15
Conclusions And Results:
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