ECE484 HW #3 FALL 2014

ECE484 HW #3 FALL 2014
Assigned: Mon. October 6, 2014
Due: Wed October 15, 2014
You will need to use the TSMC process parameter handout in order to solve these problems.
PROBLEM #1
Compute the lumped capacitance (C), the lumped resistance (R), the capacitace per unit length (c),
and the resistance per unit length (r) of a wire with the following attributes:
M3 running over the substrate. The width of the wire is 4 μm and the length of the wire is 9000 μm.
Rsh := 0.07Ω
Lw := 9000μm
Ww := 4μm
Lw
Rw := Rsh 
= 157.5 Ω
Ww
Ca := 0.011
r :=
fF
Cp := 0.042
2
μm
2
Aw := Lw Ww = 36000 μm
Rw
Lw
= 0.02
fF := 10
- 15
F
Ω
μm
fF
μm
(
)
Pw := 2  Lw + Ww = 18008 μm
Cw := Aw C a + Pw Cp = 1.15 pF
c :=
Cw
Lw
= 0.13
fF
μm
PROBLEM #2
What is the lumped capacitance between a M5 wire and a M1 wire running directly on top of one another?
The M5 wire is 10 μm wide and 8000 μm long. The M1 wire is 10 μm wide and 5000 μm long.
Lw := 5000μm
Ww := 10μm
Ca := 0.007
fF
2
Cp := 0.025
μm
2
Aw := Lw Ww = 50000 μm
Cw := Ca Aw + Cp  Pw = 600.5 fF
(
)
Pw := 2  Lw + Ww = 10020 μm
fF
μm
PROBLEM #3
What is the resistance of a M2 interconnect which is 250 μm long and 1.2 μm wide?
There is a single contact to M1 on one end and a single contact to M3 on the other end.
Do the problem again, assuming 10 contacts on each end of the wire.
Rsh := 0.07Ω
Lw := 250μm
Ww := 1.2μm
M1 to M2 contact is 2.66 Ohms.
M2 to M3 contact is 5.4 Ohms.
Lw
Rw := Rsh 
= 14.58 Ω
Ww
Rcontacts := 2.66Ω + 5.4Ω = 8.06 Ω
R := Rw + Rcontacts = 22.64 Ω
Redo the problem assuming 10 parallel contacts on each end of the wire.
Rcontacts :=
Rcontacts
10
= 0.81 Ω
R := Rw + Rcontacts = 15.39 Ω
PROBLEM #4
For a resistive NFET whose length is 10 μm and whose width is 2 μm, compute the following:
CGS, CGD,CSB.
Repeat for a saturated NFET.
LN := 10μm
WN := 2μm
2
AC := LN WN = 20 μm
For a resistive FET
Ldiff := 0.6μm
Cox := 6.079
fF
2
μm
Col := 0.599
fF
μm
CGS :=
CGD :=
1
2
 C ox AC = 60.79 fF
1
2
 Cox AC = 60.79 fF
For a saturated FET
CGS :=
2
3
 C ox AC = 81.05 fF
As agreed upon in class this semester!
CGD := 0
For either a saturated or a resistive FET.
CSB := WN Ldiff  1.699
fF
2
μm
fF
+ 2  WN + Ldiff  0.319
= 3.7 fF
μm
(
)
PROBLEM #5
What is the capacitance per unit length and the resistance per unit length of a M3 wire which runs over the
substrate?
The wire is 15,000 microns long and 2 um wide.
fF
Ca := 0.011
2
Cp := 0.042
μm
Ww := 2μm
fF
Rsh := 0.07Ω
μm
Lw := 15000μm
2
(
)
Aw := Ww Lw = 30000 μm
Pw := 2  Lw + Ww = 30004 μm
Cw := Ca Aw + Cp  Pw = 1.59 pF
cw :=
 Lw 
 = 525 Ω
 Ww 
Rw := Rsh  
r :=
Cw
Lw
Rw
Lw
= 0.11
= 0.04
fF
μm
Ω
μm
PROBLEM #6
What is the lumped capacitance to GND for a NWELL that is 5 μm long and 7.5 μm wide?
What is the resistance one would measure between the two ends of the NWELL?
Ca := 0.062
fF
Rsh := 1133Ω
2
μm
Wwell := 7.5μm
2
Lwell := 5μm
Awell := Lwell Wwell = 37.5 μm
C := Awell C a = 2.32 fF
 Lwell 
Rwell := Rsh  
 = 0.76 kΩ
 Wwell 
PROBLEM #7
What is the thickness of the field oxide which separates M2 from M1?
Field oxide is made of silicon dioxide.
- 14 F
εSiO2 := 3.9 8.54 10
Ca := 0.040
cm
fF
2
μm
tox :=
ε SiO2
Ca
= 0.83 μm
PROBLEM #8
What is the thickness of the M3 metal layer? Assume the resistivity of the M3 layer is 2.7 x 10-8 Ω-m.
Rsh =
ρ
t
Rsh := 0.07Ω
-8
ρ := 2.7 10
t :=
ρ
Rsh
Ω m
= 0.39 μm
PROBLEM #9
What is the delay associated with a 2500 μm long, 1 μm wide poly (with silicide) wire running over the substrate?
What is the delay of the same interconnect for the non-silicided case?
Rsh := 3.9Ω
Ww := 1.0μm
Lw := 2500μm
3
2
Aw := Lw Ww = 2.5  10  μm
Ca := 0.102
fF
2
μm
Lw
3
Rw := Rsh 
= 9.75  10 Ω
Ww
1
τw :=  Rw Cw = 1.24 ns
2
For the non-silicided case
Lw
5
Rw := Rsh 
= 4.42  10 Ω
Ww
1
τw :=  Rw Cw = 56.39 ns
2
tpd := 0.69 τw = 38.91 ns
2
Cw := Ca Aw = 2.55  10  fF
tpd := 0.69 τw = 0.86 ns
Rsh := 176.9Ω
PLY+BLK column!
PROBLEM #10
You are designing a clock distribution network in which it is critical to minimize skew
between local clocks (CLK1, CLK2, and CLK3). You have extracted the RC network
illustrated below which models the routing parasitics of your clock line. Initially, you
notice that the path to CLK3 is shorter than to CLK1 or CLK2. In order to
compensate for this imbalance, you insert a transmission gate (TGATE) in the path of
CLK3 to eliminate the skew. You model the TGATE as a resistance R3.
a.
Write expressions for the time-constants associated with the delays from the
clockdriver input and the output nodes: CLK1, CLK2 and CLK3. Assume the
transmission gate can be modeled as a resistance R3.
b.
If R1 = R2 = R4 = R5 = R and C1 = C2 = C3 = C4 = C5 = C, what value of R3 is
required to balance (make equal!) the delays to CLK1, CLK2, and CLK3?
( a)
For CLK1 output
(
)
(
)(
)
(
)
(
)(
)
(
)
τeq1 = C1 + C3  R 1 + C2 + C5  R1 + R2 + C 4 R1 + R2 + R4
For the CLK2 output
(
)
τeq2 = C1 + C3  R 1 + C4 + C2  R1 + R2 + C 5 R1 + R2 + R5
For the CLK3 output
(
)
(
τeq3 = C1 + C2 + C4 + C5  R 1 + C 3 R1 + R3
(b)
)
τeq1 := 9  R C
τeq2 := 9  R C
τeq3 := 5  R C + R3  C
In order for all delays to be the same,
R3 := 4  R

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