3rd SDM with FDPA Technique to Improve the Input Range

Recent Advances in Electrical and Electronic Engineering
3rd SDM with FDPA technique to improve the input range
Ik-jun Kwon, Seong-ik Cho
Electronic Engineering
Chonbuk National University
567 Baekje-daero, deokjin-gu, Jeonju-si, Jeollabuk-do
Republic of Korea
[email protected]
Abstract: - In this paper, 3rd SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input
range is proposed. Conventional architecture with 3rd transfer function is just made as adding a digital delay
path in 2nd SDM architecture. But the input range is very small because feedback path into the first integrator is
increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so
input range could be improved about 9dB. The 3rd SC SDM with only one operational amplifier was
implemented using double-sampling technique. the proposed SDM is designed in 0.18㎛ CMOS technology
with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz.
Simulation results show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of 700㎼ and Dynamic
Range of 82.8dB.
Key-Words: Sigma-delta modulator, Noise-shaping, feedback, Double sampling, SNR, Low power
SDM architecture with FDPA(Feedback Delay Pass
Addition) technique of eliminating the analog
feedback pass and implementing digital feedback
pass[5] can be operated only two clock, so can
increase the order with fewer clock than existing
architecture.
The problem of conventional architecture with
FDPA technique is that input range becomes small
as feedback pass into the first integrator is
increased. In order to improve this, in this paper,
SDM architecture with FDPA technique to improve
the input range is proposed, and The 3rd SC SDM
with only one operational amplifier was
implemented using double-sampling technique.
This paper is organized as follows. Conventional
architecture and proposed architecture are compared
in Chapter 2. The input range improvement through
MATLAB modeling and circuit improvements is
described in Chapter 3. The simulation and
discussion got a write up in Chapter 4, and the paper
is concluded in Chapter 5.
1 Introduction
Recently, in the field of audio ADC using sound,
efforts to minimize noise and to have high
resolution and low power consumption are
continued, Sigma-Delta ADC has an architecture
that satisfies both low-power and high resolution[1].
Sigma-Delta ADC consists of SDM of Analog part,
Digital Filter and Decimator of Digital part. Among
them, SDM can be realized a high SNR(Signal to
Noise Ratio) using over-sampling and noiseshaping.
Method that increases the over-sampling ratio and
the number of order of the integrator [2], [3] can
obtain a high SNR of SDM, but has the
disadvantage of increasing area and power
consumption.
Accordingly, in order to reduce power consumption
at the same time have a high resolution, feedback
the analog pass which is the output of integrator, a
digital pass which is the output of the comparator,
and increased the order of STF(Signal Transfer
Function) and NTF(Noise Transfer Function).[4]
However, as increasing the number of feedback
pass, implementation of SC(Switched Capacitor)
SDM is complicated and power consumption is
increased. Moreover, the case of analog pass, the
delaying architecture is complicated and requires
four clock in addition to the two clocks, so to share
the
operational
amplifier
using
double
sampling[6][7] is limited.
ISBN: 978-960-474-399-5
2 SDM architecture
2.1 Conventional architecture
Fig 1 shows block diagrams of 1st and 2nd
CIFB(Cascade of Integrators with distributed
FeedBack) SDM architecture.
One of the integrator is used, the 1st function is
made, and two of the integrator is used, the 2nd
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Recent Advances in Electrical and Electronic Engineering
The architecture of Fig 2 has the same SNR as the
3rd SDM, but the input range is very small because
feedback pass into the first integrator is increased.
function is made, so the order is determined in
accordance with the number of integrator.
A lot of power is consumed because the number of
integrator should be added in architecture whenever
increasing the order of the transfer function.
2.2 Proposed architecture
Fig 3. Block diagram of proposed architecture
(3)
Fig 1. Block diagram of conventional 1st, 2nd sigmadelta architecture
(4)
Fig 3 shows the proposed architecture to increase
the input range of picture 2 architecture. The input
range become small as feedback pass into the first
integrator is increased. So proposed architecture
change feedback pass into the first integrator to the
second integrator. Transfer functions of the
proposed architecture show the equation (3), (4). In
the same way as the existing architecture, the
denominator order of the transfer function was
increased using the delay element z-2 in digital
feedback pass and the numerator order of the STF
was increased using the feed-forward pass. The
proposed architecture can have a 3rd SDM
characteristics because same the order as existing
architecture, at the same time, can have an improved
input range by changing the feedback pass.
Fig 2. Block diagram of conventional architecture
Fig 2 shows SDM architecture of having 3rd
characteristics by adding input feed-forward pass
and digital delay pass with the delay elements z-2.
Because the order is increased without increasing
the number of integrators, so the power
consumption can be reduced by that much. The STF
and NTF of the Fig 1 show the equation (1), (2).
When the feedback coefficient c0 has 0, this
architecture has 2nd order transfer function. The
denominator of the transfer function can be created
from 2nd order to 3rd order by c0. However, the
order of numerator is maintained and only the order
of denominator is increased, the size of the STF in
the signal-band can be reduced.
To prevent this, by using feed-forward coefficient
g as the equation (1), the numerator order of STF
can be made and STF size in the signal-band can be
held to 1.
3 Circuit Design
3.1 Modeling using MATLAB
In order to design SC SDM applying proposed
architecture,
MATLAB
Simulink
modeling
conditions were set as shown in Table 1.
Table 1. Modeling condition of proposed
architecture
Sampling
2.8224
Frequency[MHz]
Over Sampling Ratio
64
Signal Bandwidth[kHz]
0.02-20
DC Gain[dB]
≥ 60
GB[MHz] (CL=4pF)
≥ 15
(1)
(2)
Slew Rate[V/㎲]
ISBN: 978-960-474-399-5
212
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Recent Advances in Electrical and Electronic Engineering
DAC
1bit
To obtain the coefficient values of the proposed
architecture on equal conditions with Fig 2, to give
the same input 0.5Vpp and the output range of the
first integrator and the second integrator was set to
± 0.3V as shown in Fig 4. The coefficient values
obtained by these conditions are shown in Table 2.
Table 2. Coefficient values of SDM
Coefficient
a0
b0
c0
a1
Conventional
Proposed
0.4
0.2
b1
b2
0.05 0.5 0.25
0.25 0.25
g
0.1
0.5 0.25 0.1 0.1
Fig 5. Dynamic range of Conventional architecture
and proposed architecture
The input value when the conventional architecture
has a maximum SNR is 270mV, and the input value
when the proposed architecture has a maximum
SNR is 620mV. As a result, the normally operative
maximum input improved 350mV(about 9dB) than
the conventional architecture. By the equation (5),
the input value when the architecture has a
maximum SNR is increased, dynamic range is also
increased. Dynamic Range of the proposed
architecture is about 82.8dB, approximately 3.7dB
increased than 79.1dB of the conventional
architecture.
Fig 4. Output Range of 1st and 2nd Integrator
3.2 Modeling using MATLAB
It is difficult to make sure how much change the
input range just with comparing the coefficient
value of the existing architecture and the proposed
architecture. Therefore, Dynamic Range was used to
compare the input range.
Dynamic Range is the level difference of
maximum and minimum signal measured by
measurement system at the same time, we can know
the input range of operative SDM through Dynamic
range. The SNR graphs of the existing and proposed
architecture for comparison with the input range are
shown in Fig 5, and Dynamic Range can be
obtained by the equation.
3.3 Implementation of SC SDM
In this paper, as shown in Fig 7, The 3rd SC SDM
with only one operational amplifier was
implemented using double-sampling technique,
because the power occupied by the operational
amplifier is high. The operation principle of the
circuit is as follows.
When the clock is Φ1, 1st integration about the
input signal Vin and feedback signal D·Vout is
operated and at the same time, the capacitor used for
the 2nd integration is charged. When the clock is Φ2
after 1st integration, 2nd integration about the
parameter g and the output signal Vout of 1st
integration is operated and at the same time, the
capacitor used for the 1st integration is charged. z-2
can be made simply by using D F/F and the delay of
comparator. As shown in Fig 6, was used as only
two non-overlapping clocks.
(5)
Fig 6. Used clock in proposed architecture
ISBN: 978-960-474-399-5
213
Recent Advances in Electrical and Electronic Engineering
Fig 8. Operational amplifier
4 Experiment Result
Figure 9 is results of MATLAB Simulink
simulation and Spectre simulation in 0.18 ㎛ CMOS
technology with power supply voltage 1.8V, signal
bandwidth 20KHz and sampling frequency
2.8224MHz and OSR 64-fold, respectively, 83.8dB,
81.5dB SNR is obtained. The difference of this
2.3dB is considered due to non-ideality of switch
and op-amp to configure SC integrator, and the
KT/C noise according to the size of the first
capacitor. Comparing SNR, power consumption,
and input range of standard 3rd architecture, the
conventional architecture, and the proposed
architecture are summarized in Table 4.
Fig 7. Circuit of proposed architecture
3.3 Operational amplifier design
The operational amplifier applied Fig 7 was
designed fully differential folded cascode that have
a high-gain and operate low-power and no need for
frequency compensation capacitor and have PMOS
input resistant to noise. Also, Common Mode
FeedBack(CMFB) circuit with Switched-Capacitor
architecture is designed to stabilize the output
voltage of op-amp. The performance of the
operational amplifier shown in Table 3.
Table 3.Performances of operational amplifier
OTA
DC-Gain[dB]
88
GB[MHz] ( =4pF)
18
Phase Margin[degree]
60°
Output Swing[V]
1
Slew Rate[V/㎲]
13
ISBN: 978-960-474-399-5
Fig 9. PSD Result of proposed SDM
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Recent Advances in Electrical and Electronic Engineering
[4] J. Koh, Y. Chio, and G. Gomez, “A 66dB
DR 1.2V 1.2mW single-amplifier doublesampling 2nd-order △∑ ADN for WCDMA
in 90nm CMOS,” in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, Feb.
2005, vol. 1, pp. 170-171.
Table 4.Comparison of conventional architecture
and proposed architecture
Standard Conventional Proposed
SNR(dB)
82
79.5
83.8
Power
Consumption(㎼)
900
720
700
Dynamic
Range(dB)
82.8
79.1
82.8
Maximum Input
Amplitude(V)
0.7
0.27
0.62
[5] Eui-hoon Jung, Jae-Bung Kim, Seong-ik
Cho, “Design of Opamp Sharing SDM with
FDPA(Feedback Delay Path Addition)
Technique” Journal of IKEEE, v.17, no.4,
511-516, Dec., 2013.
[6] Chuc K. Thanh, Stephen H. Lewis, and
Paul J. Hurst, “ A Second-Order DoubleSampled Delta-Sigma Modulator Using
Individual-Level Averaging” IEEE J. SolidState Circuits, vol. 32, No. 8, pp. 12691273, Aug. 1997.
4 Conclusion
In this paper, to improve the input range of the
conventional 3rd SDM with FDPA technique,
structure with improved feedback path is proposed.
The input amplitude and dynamic range of proposed
structure is 9dB(350mV), 3.7dB increased than the
conventional structure because the feedback path
into the first integrator is decreased.
The 3rd SC SDM with only one operational
amplifier was implemented using double-sampling
technique. the proposed SDM is designed in 0.18 ㎛
CMOS technology with power supply voltage 1.8V,
signal bandwidth 20KHz and audible sampling
frequency 2.8224MHz. Simulation results show
SNR(Signal to Noise Ratio) of 83.8dB, the power
consumption of 700 ㎼ and Dynamic Range of
82.8dB.
[7] D. Senderowicz, et al., “ Low-Voltage
Double-Sampled ΔΣ Converters,” IEEE J.
Solid-State Circuits, vol. 37, pp: 12151225, Dec., 1997.
References:
[1] Peluso, V. Vancorenland, P. Marques,
A.M. Steyaert, M.S.J. Sansen, Willy. “ A
900-mV low-power ΔΣ A/D converter with
77-dB dynamic range” Solid-State Circuits,
IEEE Journal of Volume: 33, Issue: 12
1998.
[2] Pin-Han Su and Herming Chiueh, “ The
Design of Low-Power CIFF structure
Second-Order Sigma-Delta Modulator ” ,
IEEE T. Circuit and Systems, MWSCAS
2009.
[3] Xi Gou, Yi-ran Li, Jian-qiu Chen, Jun Xu,
Jun-Yan Ren, “A Low Power Low Voltage
16-bit ∑△ Modulator”, IEEE T. Circuits and
Systems, ISCAS 2009.
ISBN: 978-960-474-399-5
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