SURE: Shizuoka University REpository http://ir.lib.shizuoka.ac.jp/ Title Author(s) Citation Issue Date URL Version A Switched-Capacitor Multiplier/Divider with Digital and Analog Outputs Watanabe, Kenzo; Temes, Gabor, C. IEEE Transactions on Circuits and Systems. 31(9), p. 796-800 1984 http://hdl.handle.net/10297/3447 publisher Rights This document is downloaded at: 2015-02-01T00:47:26Z 7，6 lEEJ：T≠ANSACnONSONCI CUITSANDSYmNS，VOL・C＾S−31，NO．9，SEPTuEJL1984 TranSaCtionsBriefs AS鵬仙伽i加M仙御伽I／Didkr鵬血Di虚血I andAndogOu叫血 d血血血k戚喝血kt叫鵬血町叫椚戯曲kMOSt叫・ Antxl血血虻l鷹山dm血Ⅶh此血t劇．¶絶代別鵬日脚劇m戚Hk 〆nd陶戚叩肝■触れ． XENZOWATANABE▲NDGABORC．TEMES 鵬〝坤〟−A wd罰d岬dml血lS叩岬SdI肝鵬がtd m叫k鵬肋l■血卜心頭血細．¶■i叩鵬（t¶I 血町nⅧ血ホ）脈Ii帽t ∞れ▼dd細山血樗血岬騨S吋Ⅱ棚d叫・馴叫鱒itW岬叩y鼠 Thn，肌鵬p駄鵬棚併戯鳴血山岳匹膚α血』か托せm血拐td■呼Sb 叩鵬鵬鵬仰げm伽如血eIⅣmd肌血喝▼鵬呼．椚叫，伽 血仙喝袖山喝▼咄isw摘め■叫仙山hr吋拙dYe ▲押m血鵬脚叫嘲（▲′D）伽什▼相加l・Am●W帥dy鹿川威喝 血日加叩 ∞n胱l▼血叩触れ』終曲αm血■1仇愉…yis Man血ptn鷺dvedApdL8，19糾；代Yi舞d軸kmber23，19＄3・Tbsp叫声r wasb鮎亡donw止5叩pOndhp孤nby也亡N血0血＝艶im∝Fo皿da的n undcrGrantECS810516も． 鷺．Wal血kwi血tkR離山lns山ut亡Of肋tronics，S血obU血YCト 由り．Hamumbu432，J叩an・ G．C．TtmesiswiththcD印artJTKntOEBcctricdb嘘noC血喝，Univcrsityof Cdibmi＆．LosAn鉾ks，Los血増血S，CA冥X）24・ Ⅰ．IN¶旧DUCnON Tk u父Of噌td叫u拐tOperbm血epm血g of andog或関山誌00m肌praCdce．b也e pre＄亡nt WO止，姐 attenq）tis znade to perbrn the reYerSe；an aJlal08Circuilis d∞dhdwhdcan匹rbnn血＝肌地p駄血or仙鹿ionofNや 血由td虚騨曲．U駆d＄impbおad由hlmd呼止ero灯心心血r，也e CircuitisinLtrior to aJlallJi由td staSC PCrfbmi血 血e same hncdonin tcrtmofqpcr＆血gSPCed．AIso，it znayrequiEe aS muChornoresihconarea（hspiteoEitssiznplerstructure）asits 血由tdoountαp山．Itis，bower，mu血mo托Ve指a山C：血esame drcuitcwznuldpbOrdividctwodi由talnu血krs，aJldtheoutput is availabIeinbodlaZlaloganddi由tdEbrtm．Inaddidon，the dr血tc皿pe血m鮎ap叩騨餌nmable胡mp址Cr，Or d也era 咄匝lband喝（D／A）oran血喝tO血由血（A′D）conve此r・ 0098・刷／84／0柵・07％‡01．00◎19糾IEEE 797 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS，VOL．CAS−31，NO．9，SEPTEMBER1984 0 W W 叫 （ C q ・C b ） ヒ ！ ． ＿ ＿ 」し＿ ＿ ▲ 。． ． 芝 ． 三 上一 P l・M C tDA ◆l I ◆両 はS ◆l I SSて 苑 嘩 畢 ＿P 2 暮M C IA D ◆●I ◆記 tD A ●l I 扁モ P 3 ●O A ● l l せ C ん 階 事 辿鎚 ◆ 紆 上仙 伽 T Xl■−XM O DA j仙 。一一JF→ Cx （b） Fig・1・Anm−bitprogrammablebinary−Weightedcapacitorarray（a）andits Symbol（b）． Finally，it canreadily be modified to act as a high−aCCuraCy CaPaCitanCebridgewithdigitalread−Out，aSwillbedescribedina forthcomngpublication． Itishopedthatthiscircuitwi11alsoserveasanillustrationof thepotentialsofhigh−aCCuraCyMOSanalogcircuitryingeneral Signalprocesslng，analog，digital，Orhybrid． DAAD DA SS SS 朝1 （b） II．CIRCUITDESCRIPTION Inwhatfollows，Xandyarebinarynumbersm−bitandn−bit long，reSPeCtively，lntheforms Fig・2・（a）The schematic diagramOfthe switched−CapaCitordigitalmulti− plier／divider，WhereAD，DA，and SSarethestatesignalscontrollingits Operation．nLeirtimingsequenceisshownin（b）． J＝ズ1・2−1＋ズ2・2￣2＋…＋ズ椚・2￣椚 （1） γ＝八・2￣1＋γ2・2￣2＋…十九・2￣〃． （2） Thesignsofxandyarerepresentedbytheadditionalbitsxm＋1 and凡．1，reSPeCtively，Whichassumethevalue“1’’whenxand yarenegativeand“0’’whentheyarepositive・Tbeoperation the RESETsignalsent fromaneXternaldevice toinformthe Circuitofthereceiptoftheprevi0usreSult・UponrecelVlngthis Signal，thecircuitclearSthez reglSterand，attherisingedgeof the￠clocksignalimmediatelyfollowingit，temiatestheOUT State andimitiates the DA substate of the XEC state．This executedisx・yOrX／y．Whenmultiplicationiscarriedout，Xis Substatelastsonlyoneclockperiod，tObefollowedbytheAD themultiplicandandyisthemultiplier・Tbeproductzisstored Substate．TheADstatelasts m＋n＋lclockperiod．Afterone in’aregisterof（m＋n）−bitlength．Whendivisionisperformed，X isthedividendand yisthedivisor．ToavoidanOVermow，the diviSorylSnOrmalizedsothatitsMSB，yl，isl．Tberatiois trunCatedto（m＋n）bits，andisstoredinthez register．Each numbercanbeconvertedtotheappropnatechargebymeanSOfa ClockperiodintheDAstate，thecircuitreturnsagalntOtheOUT State・Thisstatecontinuesunti1thenextRESETsignalstartsa newcycleofoperation． TbemodecontroIMC signalin Fig．2（a）selects the actual Operationperformed・WhenMC＝1，thecircuitexecutesmultipli− binary−Weightedcapacitorarrayll】，aSShoYninFig・1・Ths COnVerSionisthebasisofthedigitaloperationlnVOIvedhere． Fig・2（a）showstheschematicdiagramOftheoverallcircuit．It CPnSistsbasicallyofthreepartS；theD／Aconverter，thesucces− SIVe−q）PrOXimation A／D converter，andthe samPle and hold Cation，and when MC＝1，it performS division．Tbe detailed descnptlOnOftheoperationisglVenneXt． 」．肋〟￠〟C加わ乃 （S／H）circuit・nLeD／Aconverterisformedbythecapacitor Sincenow雨空＝0，thecapacitorsClandC2（Fig．2（a））are arraySCr，q，andC；，thefeedbackcapacitorsClandCi，and COnneCtedinparalleltoformafeedbackcq）aCitorCFOfvalue the op−amP Al．Ths converter also formS the successive− 2mC．TbecircuitconngurationintheDAandADstatesarethus approximationA／DconverterincoQiunctionwithop−amPA2 asshowninFig．3（a）and（b），reSPeCtively． andthe（m＋n）−bitshiftregister（Zregister）． Thecircuitcanbeinoneoftwostates；theXEC（execute）state duringwhichthedigitaloperationisbeingexecuted，OrtheOUT （OutPut）state dming whichthe resultis availableinthe z reglSter．TbeXECstateisfurtherdividedintotheDAandAD Sub−StateSduringwhichtheD／Aconversionandthesuccessive− approximationA／DconversionarePerformed，reSPeCtively．The dJ．（わemJfo〃山鹿以gJdJe Tbemultiphcandx programsthearrayq tosetitsvalueto 2mCx・Op−amPAlwithcapacitorsqandCFformSanOffset−free D／Aconverterl2］，【3］・Itconvertsthevalueofxintotheanalog VOltage fl by charglng q tO the scaled reference voltage CkV／（CLtCb）inthe￠＝lphaseandthendischargingitinto CFinthe￠＝1phase・TheoutputvoltageofAlisthen COrreSPOnding“state’’signalSandtheselectionsignalSSofthe reference sources controlthe operation ofthe circuit・Tbeir timingisshowninFig．2（b）．Tもeoperationcycleisimitiatedby q Gり Gり K＝石●百7㍍＝ズ石了石 （3） 798 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS，VOL．CAS−31，NO．9，SEPTEMBER1984 CF 幽W （b） （a） （b） （a） Fig・3・Circuitconfiguratipnsformultiplication：（a）TbeD／Aconverter（DA State）．O））TbesuccessIVe−aPprOXi皿ationA／Dconverter（ADstate）・ Fig．4．Circuit con丘gurations for division：（a）ne D／A converter（DA State）・（b）Tbesuccessive−aPprOXimationA／Dconverter（ADstate）． ftisappliedtothetopterminaloftheparal1el−COnneCtedcapaci− holds，Where torsGandCか Op−ampA2isconnectedasavoltagefollowerwithagrounded lnput・Itsoutputisthusitsownlnput−referredoffsetvoltageIて2 andthisisappliedtothebottomtemialsofGand Cb．The VOltage鴨acrossCbisTt一巧2，Whichwi11beapplied，inseries withtheoffsetvoltageofA2，tOthenoninvertinglnPutteminal OfA2inthesubsequentADstate． d−2．（わemJわ乃血血dpgねJe Themuldphery programSthearrayq tOSetitsvalueto 2mq′．Tbea∫rayGisnowaccessedbythe m MSB’softhe eJ＝Gり （7） ez＝G〟り＋G／り／2〝 ＝（zl・2￣1＋Z2・2￣2＋…十g朋．〃・2￣（∽＋〝））2椚C・り ＝G巧． （8） The（m＋n）−bitshiftregisterthusstorestheproductz三＝X・y． 月．且肋血血椚 z register．Tberema皿ngnbitsofthezregisterprogramthearray C；／．TbesetwoaLraySformincombinationthearrayC；forthe PrOductz・Op−amPAlandthearraySGandq，nOWforman Offset−freeD／Aconverter．Tbec叩aCitorsGandCbareinthis StateCOnneCtedinseries；theirinitialvoltageisI左，aSaCquiredin thepreやusDAstate・Op−amPA20PerateSaSaCOmparatOr・・The WholeclrCuit，hcludingthe z register，nOWformSaSuCCeSSive− approximation．mitiplyingA／Dconverter（Fig・3（b））・ neconverslOnbeginsafterCFisdischargedinthe7もperiod Inthisoperation，MC＝1and，therefore，thecapacitorCiis Short−Circuited．The circuit configurationsinthe DAand AD StateSarethenasshowninFig．4（a）and（b），reSpeCtively．During theDAstate，thearraysClandqaresettothevalues2mCX and2mCy，reSpeCtively．TbesetwoarraySandop−amPAlforman Offset−freeD／Aconverterwhichconvertstheratiox／yintothe analog voltage ft／，by charglng q tOthe scaled reference VOltageCJft／（Ci＋Cb）inthe￠＝lphaseandthendischarging itintoqinthe￠＝1phase・Tbeoutputvoltageofop−ampAlis （Fig・2（b））・IntimeslotTl，thecapacitanCeOftheamayqisset to2m．lcbyassumngtemporarilyzl＝landischargedtothe referencevoltageりinthe￠＝lphase．Theinputvoltagennof Kル＝器・号・ （9） thecomparatoristhentheweightedsumOfthepresentoutputq OfAl，thevoltageacrossCb，andtheoffsetvoltageofA2： nLuSIも＝ft／y一巧2isgeneratedasdescribedinSectionII−A−1・ InthesubsequentAI）state，theanalogvoltagefl／，lSCOn− 巧n＝藷が＋…2＝盈（云一号）・（4） Tbe offsetvoltage of A2does not appearin（4）becauseitis CanCelled．TbeoffsetvoltageofAlisnotincludedeither，because Ofthe offset−free D／Aconversion．Tbecomparisonprocessis， therefbre，Offset free．Depending onthe polarity of nn，the COmParatOrA2keepszlaSl（ifnnispositive）orresetszltOO （if nnisnegadve）． Inthenextti皿eSlot T；，thecapacitoroftheamyC；corre− SPOnding to22lS aCCeSSed simi1ady，Whlethe value of zlis StOred．nnisnow Vertedtoan（m＋n）−bitnumberzbythesuccessivF−aPPrOXimチー tionA／DconvertershowninFig・4（b）・TもeconverslOnPrOCeSSIS thesameaSthatdescribedinthemultiplierandisagalnPraCti− Callyoffset−freeiftheopen−loopgalnSOfAland A2areVery high．TbechargeonCbisnowapproximatelybalanCedsothat 臥 eZ ■■■l q q （10） holds，WhereCF＝Cl＝2m−lcandQ，andQzaregivenby（7） and（8），reSPeCtively．The ratio z rounded to（m＋n）bitsis StOredinthez reglSter． ThecircuitinFig．4canaccomplishotherfunctionsaswell．If， e・g・，ananalog signal巧is apphed at the temialwhere the SCaled reference voltage CkTt／（G＋Cb）was previously con− q zl・2椚￣lc＋2椚￣2C CF q nected，then nominvertlnganPlificationwitha programmable ）・（5） gainx／yisobtainedbythecircuitofFig．4（a）．nesuccessive一 A2keepsz2aSlif nnispositiveandresetsz2tOOotherwise． 叩PrOXimationA／DconvertershowninFig．4仲）thenprovidesa digitaloutputzsuchthat Thsprocessisrepeated（m＋n）times，unti1achargebalanCeis reachedonCbSOthat 可…・器巨 （11） eJ eZ CF q （6） holds．Therefore，ifxand y aresetsothattheparenthesized 799 IEEETRANSACTlONSONCIRCUlTSANDSYSTEMS，VOL．CAS−31，NO．9，SEPTEMBER1984 Fig・6・The schematic diagramOfthe multiplier circuitincluding theim− portantParaSiticelements． ＼血 （b） Fig・5・CircuitconEigurationsforanalogoutput：（a）TbeD／Aconverterin the7L汁n＋lperiod・（b）Tbesampleandholdcircuit． factorFqualsl，thedivideraccomplishesan（m＋n）−bitA／D COnVerSlOn． III．ANALOGOUTPUT Ineithermultiplicationordivisionoperation，the circuitre− turnstotheDAstateattheonsetofthe Tn＋n＋l Period．The・ CircuitdiagramOfthestagecontalnmgAl，Validinthisperiod，is Shownin Fig．5（a）．ItisanOffset−free（m＋n）−bitI）／A con− isalso true forthose gate−SOurCeand gate−drain feedthrough CaPaCitancesoftheMOSswitcheswhichareCOnneCtedbetween VOltage sourcesand ground only．FurthemOre，SOme Ofthese feedthroughcapacitanCeSareCOnneCtedtothesamenOdesand drivenbythecomplementaryclocksignalS，SuChasCLandC；in Fig．6 These paired capacitanCeS Can bealso neglected to a 且rst−Orderapproximation．Onthebasisoftheabove，WeObtain thecircuitinFig．6asthepractiCalcircuitmodelofFig．2（a）． ReferringtoFig．6，WeCanObtaintheexpandedchargebalanCe equation Cり・G／（G＋Cぁ）＋q均＋（q＋q＋q）巧1／（1＋dl） q（1＋叶等）） G ez＋Aez−q均一（C＋q＋q）巧l／（1＋dl） ＝0．（12） 耶＋G q（1・叶等）） Verter，PrOvidingthe analog voltageI乞＝lzIV which canbe Here，TtistheamPlitudeofthecl∝ksignalappliedtothereset SチmPledandheldbytheaddedcircuitshowninFig・5（b）・Ths ClrCuitformSaVOltagefollowerwhenthesignoftheproductor therati0，Sgn Z，ispositive．Whensgn zisnegative，itformSa SWitch・TheprimedcapacitanでeS（G，C；，etC・）denotetheactual ValuesincludingtheinaccuracleS，WhileAQzrepresentstheerror VOltageinverterswitchl4］andprovidestheoutputwithanega− tivepolarity．Ineitherconnection，theoutputisoffset−freebe− CauSetheoffsetvoltageofA3isdetectedandheldintheholding inQzandhenceintheoutputzduetothenomidealfactors． AdetailedanalysisofthetermSCOntributingtoAQz，0mitted intheinterestofbrevity（but availablefrom the authorsupon request），reVealSthattheexpectedcircuityield foralO−bit CaPaCitorChinthe“Sample”period，andthencanCelledinthe accuracylS about38percent；for a9−bit accuracy，about68 Subsequent“hold’’period．Tbeclockfeedthroughhasnoeffect PerCent；andfbran8−bit accuracy，about95percent．Identical Onthe output either，Since eachnodeis connected either to a VOltagesourceortoground． COnClusionsholdfortheaccuracywhenthecircuitisusedasa divider． ⅠV．ExpERIMENTALVERIFICATION ThechargebalancerelatioTSgivenin（6）and（10）donottake into account nOnidealcircult COnditions such as capacitanCe mismatch，theoffsetvoltagesandthefimitegalnSOftheop−amPS， ParaSiticcapacitanCeS，andthefeedthroughfrom theclocksig− nalS．In this section，the charge balance equation valid under PraCtiCalconditionsisglVen，tOObtainaneStimateoftheaccu− racyoftheoperation． ThecircuitshowninFig．2（a）contains，infact，manyparaSitic CaPaCitanCeS nOt Showninthe ngure．Tbose paraSitic capaci− tances，however，Whichareconnectedorswitchedonlybetweena VOltagesourceandgroundhavenoeffectontheoperation．Ths A4×4−bit multiplier／divider，based onthe scheme of Fig． 2（a），hasbeenconstruCtedushgCMOStranSmiSsiongates，an LM347JFETop−amP，and discretecapacitors．Allarrayscon− Sistedof2，1，0．5，andO．25nFcapacitors．AllothercapacitanCeS WereChosento2nF．Thesupplyvoltageswere±6V． Fig．7showsthewaveformSObservablewhenthedigitalmulti− Plication（−0111）×（1100）wasexecuted．Tbezerolevel，thecir− Cuitstates，andthetimlngarealsoindicatedinthefigure・Tbe referencevoltageりWaS3．6V．Tbeuppertraceshowsthevoltage fLatnode④duringtheXECstatefFig・2）・TbeinidalValueis thesmalloffsetvoltageofAlaPPeanngatnOde④duringthe 800 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS，VOL．CAS−31，NO．9，SEPTEMBER1984 Fig・7・Waveforms appeanng Whenthe digital du血gtheXECstate． F霊ut芝a芸荒￡駕豊霊悪邑芯三豊三豊霊 笥慧 Lowertmce：rmeOutPutVOltageofS／Hcircuit．（Theactualverticalscaleis （一0111）×（1100） WaSeXeCuted．LWertrace：nLeVOltageatnode tentimesthatindicatedinthefigure，SincealO：loscilloscopeprobewaLS trace：TbeoutputvoltageofS／Hcircuit．（Tbeactualverticalscaleis ten timesthatindicatedinthe且gure，SincealO：loscilloscopeprobewasused．） used．） ￠＝1phaseintheDAsubstateofXEC．Inthenext￠＝lphase， themultiphcand（7／16）isconvertedtotheanalogvoltageTt＝ （7／16）×（3．6／2）＝0．79V．NoticethatduringthesubsequentAD Substate，thisvoltageisheldinCbandIちisthesumof fLand halfoftheoutputvoltageofop−amPAl．Duringthe￠＝1phase in7も，0．5Vcanbeseensuperposedonflduetothedischargeof CFCauSedbyP2＝1．Inthe￠＝lphasein71，Zlistested．The VOltage yLinthisphaseisO．79−（2／3）×3．6／2三一0．41V，thus thevalue“0”isasslgnedtozl．Inspectlngthevoltagelevelsinthe Subsequent seven ￠＝l phases，We Can read the product （01010100），aSindicatedintheFigure・Thsisthecorrectaneyer・ The circuit now returns tothe DA substate and，inthe￠＝1 phase，COnVertSthe product（21／64）intothe analog voltage fL＝1．18V．Thelowertraceistheoutputy；ofop−amPA3（Fig． 5），Showing how y：is sampled，inverted sincethe sgn zis negative，andheldbytheS／Hcircuit． Fig．8showsthewaveformsobservablewhenthedigitaldiviー Sion（1000）÷（1111）wasexecuted．Indivision，theoutputvoltage OfAICanbeashighas2Tl becausetheratiozcanaSSumethe maximumvalue2．Therefore，the referencevoltage f；was re− ducedto2Vtopreventtheop−amPAlfrombeingsaturated．The timingofthetraceisthesameasthatinFig．7．Theuppertrace （thevoltageIl atnode④）showstheprocessproducingthe ratio（01000100）．Thsratiois correctup to8bits．Tbelower tracdshowshowtheratioTiinanalogformissamPledandheld bytheS／Hcircuit． bythemismatchesinthecapacitorarrayS・Numericalcalculations uslng aVai1able dataon MOScapacitorsindicate that8，9，Or lO−bitaccuracylSObtainablewith95，68，Or38percentyields， respectively． The main advantageOftheproposed circuit overaconven− tionaldigitalmultiplierisitsversatility：ItcanPerform，besides digitalandhybridmultiplicationanddivision，alsoprogramm− ableamPlificationaswellasD／AandA／Dcopversion・Tもe maindisadvantageistheloweroperatingspeed，eStumatedas2to 3times slower thanthat of a serial−Parallel CMOS digital multiplier・Inadditiontoitsversatility，theproposedcircuitcan beimplementedbyuslngarelativelysmallnumberofcompo− nents・Countlng amit capacitor as being equivalent to a MOSFET，a4×4−bit multiplier canbe built by about500 MOSFET’S・Aconventional4×4−bitserial−Parallelmultiplier，On theotherhand，requiresabout700devicesl7］，【8］．Tbeproposed Circuit，however，may require a slightlylargerarea Whenin− tegratedonSichipbecausetheanalogMOSFET，sinvoIvedinthe OP−amPSrequlrelargergateareaSthandigitaldevices．Thscan beremediedbyuslngthemuchsimplerdynamicop−ampSfirst SuggeStedbyCopelandandRabaeyl9］． AcKNOWLEDGMENT The authors are gratefulto Prof．Ken Martin ofUCLAfor usefuldiscussions・TbenrstauthoralsothankstheMimistryof Education，Japan，forsupportlnghisstayatUCLA． REFERENCES Ⅴ．CoNCLUSION ll】J・LMcCrearyaLndP・R・Gray，“Al1−MOSchargeredistributionanalog− Aswitched−CaPaCitorcircuitwaspresentedforthemultiplica− tionordivisionoftwodigitalnumbers．Theoutputisavai1ablein bothanaloganddigitalforms．TheprlnCiplesofoperationhave beenconLirmedexperimentally．TbedesigncriteriaforICrealiza− tionaresummarizedasfollows： 1）Thegainsoftheop−anPSdonotdirectlyaffecttheaccu− racy．Thsis becausethe charge balanceis achieved by the iterativeuseofoneop−amP．Therefbre，thereductionoftheoffset VOltage should be emphasizedinthe design of the op−amPS， ratherthanaveryhighgainwhichwouldalsodegradetheslew rate． 2）TomaketheunitcapacitorsinthearraySSmal1，andthereby to−digitalconversion teclmiques−PartI，”IEEEJ．SoHdStateCircuits， VOl．SC−10，pp．37ト379，Dec．1975． ［2］R，GregorianandG・Amk，‘‘Anintegrated，Single−Chip，Switched−CapaCi− torspeechsynthesizer，”hProc・Int・勘mp・OnCircuiLfandSysteJW，Pp． 733−736，（Houston，TX），1980． ［3］R・GregorianandS．Fan，“Offsetfreehigh−reSOlutionD／Aconverter，”in J4摘心肋〝∽rCo扉0〃Cfrc〟巾，伽Je冊，α〃dCo〝卯〝e〝わ，pp．316−319， Nov．1980． ［4】A・Fettweis，“Basicprinciplesofswitched−CaPaCitorfiltersusingvoltage inverterswitches，MArch・Ekk・【伽rtragung，VOl・33，Pp・13−19，Jan・1979． （5］R・E・Suares，P・R・Gray，andD．A．Hodges，“Al1−MOSchargeredistri− butionaLnalog−tO−digitalconversiontechniques−PartII，”／EEEJ．So〟d− StateCircuits，VOl．SC−10，pp．379−385，Dec．1975． ［6］K・Martin，“New clock feedthroughcancellation techmique for analog MOSswitched−CapaCitorcircuits，”肋tron・LJett・，VOl・18，pP・39−40，Jan・ 7，1982． ［7］R・M・M・Obermann，Didta／CircuitJbrBinaryArithmetic．NewYork： to savethe chip area，Clock feedthroughcancellationl5］，【6］ Shouldbeprovidedwiththeresetswitches． 3）TheholdingcapacitorsGandCbShouldbemadeaslarge aspractical・Withtheseprecautions，theaccuracyislimitedonly Halsted，1979，Ch．4． ［8】W・N・CarrandJ・P・Mize，MOS／LSIDesign andAppHcation．New York：McGraw−Hill，1972． ［9］M・A・CopelandandJ．M．Rabaey，“DynamicamplifierforMOSteclm01− Ogy，”蝕C細れエビ〟リVOl・15，pp・301−302，May1979・
© Copyright 2024 ExpyDoc
