1 - WIPO

F 032
Annex 01, page 1
A. Request for Revision of the IPC
Class(es) or subclass(es):
G06F
ELECTRIC DIGITAL DATA PROCESSING
1.
Description of the area to be revised:
G06F12/08 - G06F12/12
Hierarchically structured memory systems
2.
The request will be evaluated according to the following criteria:
Reasons for revision
A
Subdivision of IPC groups having an excessive file size
Av.- file size
> 13100
B
High rate of growth of the PCT minimum documentation
C
Due to changes in technology the classification structure has
become inefficient for searching. A gain in efficiency is
expected with the proposed new scheme
D
Clarification of wordings in order to improve consistency in
classifying or to avoid overlap with other places of the IPC
E
A high number of searches are executed in the technical
field (i.e. a high number of patent applications or a high
number of searches for other purposes)
F
New technology not specifically covered in the current IPC
Growth rate /y
patent appl.
other searches
Appropriate subdivisions already exist in a local
classification scheme and can be easily brought into the IPC
Scheme(s)
No. of subgroups
CPC
3 -> 50
Reclassification effort: No. of families to reclassify:
Mechanically, using
existing data
Intellectually
Factors influencing the cost and effort of the project
G
H
Additional Remarks
The five offices determined that each subgroup should be hierarchically developed by establishing
numbers of more detailed subdivisions in order. It is aimed at improving effectiveness of the IPC as
a search tool since, among groups G06F12/08 - G06F12/12, each subgroup contains on average a
large number of 13100 patent documents.
The proposed scheme and RCL presented in this report, agreed upon by the five offices after review
at the F032, intend to introduce hierarchically higher groups of the CPC’s groups G06F12/08 G06F12/12.
G06F12 is not presented in the CE456 list.
Proposing Office: Japan Patent Office
Date: March 7, 2014
Signature: Tomonori Kikuchi
F 032
Annex 01, page 2
B. Scheme Proposal
expected IPC
kind
IPC/CPC/FI
dot
U G06F12/02
IPC
G06F12/02
•
C G06F12/08
IPC
G06F12/08
・・
N G06F12/0802 CPC G06F12/0802 ・・・
N G06F12/0804 CPC G06F12/0804 ・・・・
N G06F12/0806 CPC G06F12/0806 ・・・・
N G06F12/0808 CPC G06F12/0808 ・・・・・
N
N
N
N
G06F12/0811
G06F12/0813
G06F12/0815
G06F12/0817
CPC
CPC
CPC
CPC
G06F12/0811
G06F12/0813
G06F12/0815
G06F12/0817
・・・・・
・・・・・
・・・・・
・・・・・・
N G06F12/0831 CPC G06F12/0831 ・・・・・・
N G06F12/0837 CPC G06F12/0837 ・・・・・・
N G06F12/084
CPC G06F12/084
・・・・・
N G06F12/0842 CPC G06F12/0842 ・・・・・
N G06F12/0844 CPC G06F12/0844 ・・・・
N G06F12/0846 CPC G06F12/0846 ・・・・・
N G06F12/0853 CPC G06F12/0853 ・・・・・
N G06F12/0855 CPC G06F12/0855 ・・・・・
N G06F12/0862 CPC G06F12/0862 ・・・・
N G06F12/0864 CPC G06F12/0864 ・・・・
N G06F12/0866 CPC G06F12/0866 ・・・・
N G06F12/0868 CPC G06F12/0868 ・・・・・
N G06F12/0871 CPC G06F12/0871 ・・・・・
N G06F12/0873 CPC G06F12/0873 ・・・・・
N
N
N
N
G06F12/0875
G06F12/0877
G06F12/0879
G06F12/0882
CPC
CPC
CPC
CPC
G06F12/0875
G06F12/0877
G06F12/0879
G06F12/0882
・・・・
・・・・
・・・・・
・・・・・
TITLE
Addressing or allocation;
Relocation(programme address sequencing
G06F9/00; arrangements for selecting an
address in a digital store G11C8/00)
in hierarchically structured memory systems,
e.g. virtual memory systems
Addressing of a memory level in which the
access to the desired data or data block
requires associative addressing means, e.g.
cache
with main memory updating (G06F12/0806
takes precedence)
Multiuser, multiprocessor or multiprocessing
cache systems
with cache invalidating means (G06F12/0815
and subgroups take precedence)
with multilevel cache hierarchies
with a network or matrix configuration
Cache consistency protocols
using directory methods
using a bus scheme, e.g. with bus monitoring
or watching means
with software control, e.g. non-cacheable data
with a shared cache
for multiprocessing or multitasking
Multiple simultaneous or quasi-simultaneous
cache accessing
Cache with multiple tag or data arrays being
simultaneously accessible
Cache with multiport tag or data arrays
Overlapped cache accessing, e.g. pipeline
(G06F12/0846 takes precedence)
with prefetch
using pseudo-associative means, e.g. setassociative, hashing
for peripheral storage systems, e.g. disk
cache
Data transfer between cache memory and
other subsystems, e.g. storage devices or
host systems
Allocation and management of cache space
Mapping of cache memory to specific storage
devices or parts of a storage device
with dedicated cache, e.g. instruction or stack
Cache access modes
Burst mode
Page mode
F 032
Annex 01, page 3
N G06F12/0884 CPC G06F12/0884 ・・・・・
N
N
N
N
N
G06F12/0886
G06F12/0888
G06F12/0891
G06F12/0893
G06F12/0895
CPC
CPC
CPC
CPC
CPC
G06F12/0886
G06F12/0888
G06F12/0891
G06F12/0893
G06F12/0895
・・・・・
・・・・
・・・・
・・・・
・・・・・
N G06F12/0897 CPC G06F12/0897 ・・・・・
C G06F12/10
IPC G06F12/10
・・・
N G06F12/1009 CPC G06F12/1009 ・・・・
N G06F12/1018 CPC G06F12/1018 ・・・・・
N G06F12/1027 CPC G06F12/1027 ・・・・
N G06F12/1036 CPC G06F12/1036 ・・・・・
N G06F12/1045 CPC G06F12/1045 ・・・・・
N G06F12/1072 CPC G06F12/1072 ・・・・
N G06F12/1081 CPC G06F12/1081 ・・・・
N G06F12/109
CPC G06F12/109
・・・・
C G06F12/12
N G06F12/121
IPC G06F12/12
CPC G06F12/121
・・・
・・・・
N G06F12/122
CPC G06F12/122
・・・・・
N G06F12/123
CPC G06F12/123
・・・・・
N G06F12/126
CPC G06F12/126
・・・・・
N G06F12/127
CPC G06F12/127
・・・・・・
N G06F12/128
CPC G06F12/128
・・・・・
Parallel mode, e.g. in parallel with main
memory or CPU
Variable-length word access
using selective caching, e.g. bypass
using clearing, invalidating or resetting means
Organisation and technology of caches
of parts of caches, e.g. directory or tag array
with a plurality of cache hierarchy levels
(G06F12/0811 takes precedence)
Address translation
using page tables, e.g. page table structures
involving hashing techniques, e.g. inverted
page tables
using associative or pseudo-associative
address translation means, e.g. translation
look-aside buffer (TLB)
for multiple virtual address spaces, e.g.
segmentation (G06F12/1045 takes
precedence)
associated with a data cache
Decentralised address translation, e.g. in
distributed shared memory systems
for peripheral access to main memory, e.g.
DMA
for multiple virtual address spaces, e.g.
segmentation (G06F12/1036 takes
precedence)
Replacement control
using a replacement algorithm
of the least frequently used type, e.g. with
individual count value
with an age list, e.g. MRU-LRU list or queue
with special data handling, e.g. pinning, errors
or priority of data or instructions
using an additional replacement algorithm
adapted to multidimensional cache systems,
e.g. set-associative, multicache, multiset or
multilevel
C. RCL
Current IPC
New IPC
Default Transfer
C
G06F12/08
G06F12/08 - G06F12/0897
G06F12/08
C
G06F12/10
G06F12/10 - G06F12/109
G06F12/10
C
G06F12/12
G06F12/12 - G06F12/128
G06F12/12
[END]

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