CS 530, High Performance Computing Homework #2 Assigned 28 April 2014; Due 05 May, 11:59pm Computer Science Introduction/Overview This homework is worth 20 points. Please submit, via Canvas, a single document, that has your answers to the following 5 questions. Be sure to show your work, for partial credit. You may use a calculator, spreadsheets, or you may write a program to help you arrive at an answer. However, the answers must be yours and yours only. Although you may discuss the homework with your fellow students, you cannot discuss solutions, as that would be a violation of the university's honor policy. Please ask Filip if something is not clear. 1. For a 32-bit computer with 4GB of main memory, 128KB 4-way associative cache with a block size of 8 bytes, answer the following: • • • • • • • • • • How many bytes are there in a cache set? How many lines are in the cache? How many sets are in the cache? How many blocks are there in main memory? How many bits wide is the tag field in main memory? How many bits wide is the tag field in cache? How many bits wide is the set field? How many bits wide is the offset field? How many bits wide is the flag field? The main memory byte at the following address would be placed into which row (set) of cache? 00010001000100010001000100010001 2. You are an employee at a computer company. A soon-to-be-completed system has the following specs: • • • • 16GB of main memory 2MB of cache with each line having 64 bytes a pipeline of depth 6 Memory-cache latency of 40ns Your task is to help design the system so that any latency (between main memory and cache) is completely hidden. To that extent, the system should be designed with what minimum bandwidth (of moving data to/from memory and cache), assuming that the system can handle (hold in a prefetch issue buffer) 6 prefetch requests? Hint: see section 1.3.3 of the textbook. 3. In lecture, we've discussed how (and why) blocks are evicted from cache. The Least Recently Used (LRU) algorithm was presented as the default method for selecting which block is evicted. However, there are other methods, including Least Frequently Used (LFU), and First In First Out (FIFO). Discuss briefly (at most one page), scenarios where LFU and FIFO would be better suited than LRU, as a cache eviction scheme. CS530 Spring 2014, CWU, Homework 2, Dr. Filip Jagodzinski page 1 of 2 4. Your task is to select one of five cache designs for a computer that is being built specifically for a weather simulation program written in Java. You have very few details about the simulation program, but you've been told that a certain subroutine X in the simulation engine/program will repeatedly cycle through arrays made up of 16,000 integers (values of type int). The computer will have no hardware nor software prefetching. Based on only these criteria, which of the following cache designs would you recommend using? Explain. If none of them are appropriate, explain why. If more than one is appropriate, select a best option, and be sure to argue and substantiate your claim. Cache Design 1 2 3 4 5 Associativity 2-way 4-way 8-way 16-way 32-way Line Size 4 bytes 4 bytes 2 bytes 2 bytes 1 byte 214 212 211 29 28 Total Rows 5. You are designing a single-chip computer, with L1 cache only. Explain briefly (at most 1 page) how large the cache should be, and how many bytes should each line contain (block size). Justify your reasoning. CS530 Spring 2014, CWU, Homework 2, Dr. Filip Jagodzinski page 2 of 2
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