Performance of the AMT-3 Based TDC System at Belle S.Y.Suzuki, T.Higuchi, Y.Arai, K.Tauchi, M.Nakao, R.Itoh (KEK) H.Nakayama (University of Tokyo) Belle experiment at KEKB Designed luminosity • • • • • Study of CP violation in B-meson decays from Y(4S) The Belle detector consists of 7 sub-detectors. L1 trigger – 500Hz(average) Data size – 40kB/ev Achieved 160% of the designed lumionsity. Schematic view of DAQ system Readout Subsystems SVD Multihit TDC ACC SVD Online farm ECL Reconstruction Farm KLM EFC Using Q-to-TTOF + multi-hit TDC technique, most of CDC detectors are read out by the same FASTBUS TRG TDC system. SEQ Except deadtime, FASTBUS is excellent. Trigger, Sequence Controll FASTBUS VME PC Present FASTBUS DAQ system • TDC – LeCroy 1877S FASTBUS – High channel density : 96ch per board – Fine resolution : 16bit x 500ps LSB, 32μsec window – Q-to-T : Multi-hit up to 16 edges per channel • Unified DAQ system : easy to maintain. • Except deadtime – No pipeline : trigger and busy hanshake in delay + common-stop Deadtime fraction (%) Deadtime fraction •Deadtime is proportional to the product of the trigger VETO for rate and the data size. injection 10Hz continuous •This deadtime comes from FASTBUS TDC. •Luminosity increase makes the higher trigger rate and larger data size. So we developed new readout system. Trigger (Hz) New DAQ concept • Pipelined readout system • Smooth upgrade path • Unified readout system Design of new readout system • Digitizer Online Processor Readout FIFO Digitizer Signals from detector – Pipelined digitization • Readout FIFO – Event buffers for asynchronous readout • Online processor – Data size reduction – Data transmission over TCP/IP Everything on a single board Schematic view of “COPPER” PMC modules PMC CPU Bridge Digitizer Trigger and busy handshake for the smooth upgrade. Network IF COPPER co-exists with present FASTBUS TDC readout. Digitizer Trigger Trigger Module Digitizer Busy Readout FIFO to event builder PCI bus Digitizer local bus from detector FIFO AMT-3 • Replacement of FASTBUS TDC with pipelined TDC • AMT-3 based TDC is implemented in the digitizer card of the COPPER. • AMT-3 chip originally developed for ATLAS – Pipeline TDC – Multiple buffers allow asynchronous readout • Channel buffer • L1 FIFO • Readout FIFO – 24ch LVDS input/chip – 780ps LSB x 17bit, 102.4μsec window – 250ps Time resolution (RMS) • Similar spec to the FASTBUS TDC, suitable for the replacement. The COPPER TDC • Add-on module for COPPER – 2 AMT-3 chips per module – 48 ECL inputs (ECL-to-LVDS converter) PLX 9054 EPC-6315 AMT3-FINESSE AMT3-FINESSE Data stream 82559 PCI bus localbus – 2 add-on modules per COPPER – 96 inputs in total – Connector shapes and signal level are compatible with LeCroy FASTBUS TDC’s. Signals from detector • COPPER TDC TT-RX (trigger receiver) trigger The COPPER TDC History of COPPER study • Since September 2005, first 6-module test setup commissioned in Extreme Forward Calorimeter. • Since September 2006, 16-module setup commissioned for the Central Drift Chamber readout. • Performance was compared with the FASTBUS system. 16-module setup Signals are digitized simultaneously by FASTBUS and COPPER for the consistency check. ShaperQT Central Drift Chamber ………… COPPER FASTBUS Signals are daisy-chained to FASTBUS via COPPER. COPPER time (ns) Data consistency FASTBUS time (ns) Linearity / Resolution # of events Difference from the expected value (LSB) RMS is 0.61LSB It is consistent with the specification of AMT-3 itself, Time resolution ~ 250ps (RMS) AMT-3 time (ns) Diff from the expected value (LSB) Deadtime improvement Deadtime (us) Nominal data size 29.5us Offset = 25usec Deadtime is < ~ 1/10 Offset = 0.72us 2.8us # of hits/TDC Summary • Higher trigger rate and larger data size are expected in near future. • We developed a new pipelined TDC to reduce the deadtime. • 1/10 shorter deadtime is achieved. (29.5us -> 2.8us) • It was proven to have sufficient performance to supersede current FASTBUS readout system. – Compatible with the FASTBUS TDC
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