A Dive into Opensource Verification Language, Vlang

A Dive into Opensource Verification Language, Vlang
Puneet Goel,
Sumit Adhikari,
Coverify Systems Technology,
Gurgaon, India
Email: [email protected]
NXP Semiconductors GmbH,
Hamburg, Germany
Email: [email protected]
Abstract—The past decade has witnessed significant broadening of
hardware verification domain. Modern Hardware Verification Languages
(HVLs), which have been drafted with a focus on RTL verification,
are facing new challenges. There is a challenge on performance front
due to a growing need to testbench Emulation Platforms and Virtual
Platforms. On the other hand language expressiveness of the HVLs is
being challenged by the increasing requirement for hardware/software coverification and verification of heterogeneous systems. In this demo we
introduce and present the next generation verification language Vlang [1].
Vlang is a multicore enabled, generic and generative programming
supportive verification language. Vlang is opensource and is built on top
of the D Programming Language [2]. It takes advantages of D’s strong
metaprogramming and reflection capabilities to eliminate boilerplate.
Vlang is Application Binary Interface (ABI) compatible with C/C++;
it creates single executable with SystemC [3]. For RTL verification it
integrates with SystemVerilog [4] seamlessly through Verilog Procedural
Interface (VPI) and through Direct Programming Interface (DPI). Currently Vlang supports Universal Verification Methodology (UVM) (1.1d
release) as verification methodology library.
I. I NTRODUCTION
Continued extension of Moore’s Law with respect to System on
Chip (S O C) transistor count has resulted in complex verification challenges. A decade back (ref Figure 1) RTL simulation and verification
tools used to automatically scale, thanks to the then healthy growth
of the processor frequency. But ever since the processor speed has
gone stagnant, and as a result verification tools no longer scale.
Also, as more and more transistors become available to the
designers, the architectural complexity of the S O Cs continues to grow
exponentially. But the tools available for implementing these designs
have remained more or less limited to RTL domain. This has resulted
in growing abstraction gap between the specifications and the design
implementation (in RTL), famously termed as Verification Gap. In
fact we have moved into an era where the designers want software
to be tested before the design is mapped to silicon.
1970
Server CPU Trends
Transistor Count(K)
CPU Clock (MHz)
Perf/Clock
1975
1980
1985
1990
1995
B. Solutions Offered by State of the Art Languages
DUT Simulation
Data Synchronisation
Testbench Simulation
SystemVerilog Cosimulation
Vlang Cosimulation
A. Problem Statement
1G
100M
10M
1M
100K
10K
1K
100
10
1
This has resulted in:
1) More and more designs being verified with help of Emulation
Platforms
2) Need to verify the design early on, using Virtual Platforms
3) A growing need for faster verification tools
2000
2005
2010
Fig. 1. Even as number of transistors in SoC continues to grow, the CPU
frequency and performance graphs have saturated
Fig. 2. SystemVerilog and DPI become a performance bottleneck when used
for implementing testbenches for Emulation Platforms and Virtual Platforms
At RTL level, the interaction between the Verification Testbench
and the Design Under Verification (DUV) is at plain old signal
abstraction. SystemVerilog provides the SV interface construct
for this purpose, which helps a verification engineer to mould a
transaction into signals and vice versa.
As verification moves to emulation platforms, the signal layer
and the corresponding Bus Functional Model (BFM) become a
bottleneck for verification performance. It has become a general
practice to synthesize the signal layer of the testbench and put
it on the Emulation Platform along with the design. As a result,
the interaction between the testbench and the DUV has now really
moved to transaction level. Virtual Platforms too need stimulus to be
provided in form of transactions.
SystemVerilog faces four challenges stated below:
1) Virtual Platforms and Emulation platforms increase the speed
of DUV simulation by at least a couple of orders of magnitude.
When SystemVerilog is used as testbench language for these
platforms, it slows down the simulation (ref Figure 2) by not
being able to stimulate the design fast enough.
2) Though SystemVerilog provides DPI, for transaction level
interaction with C/C++ Application Programming Interface
(API), which is a big improvement over Verilog Programming
Language Interface (PLI), the DPI itself has a significant
interface overhead [5].
3) Despite the “System” moniker, SystemVerilog has failed to
provide a viable medium to code at Systems Level [6]. This has
become an impediment when we consider the growing need for
hardware software co-verification.
4) Although the simulation tools have evolved in the past decade
to make multicore RTL simulation feasible, parallel testbenches
in SystemVerilog are a far dream since the language does not
provide relevant constructs to enable multicore programming
at behavioral level.
C. Vlang, the Solution for the Next Generation Verification
We introduce Vlang [1] as next generation verification language
with following salient features:
1) Clean and easy syntax (close to SystemVerilog and/or SystemC)
and yet extremely powerful (fast learning and high productivity)
2) Multicore parallelism (for faster simulation and Verification IP
(VIP) scalability)
3) N number of simulators possible in one simulation (faster
simulation, easier simulation management (no scripting))
4) Truly object oriented, supported by modern compiler technology (great design, less code, high re-usability)
5) Generic programming, template meta-programming (generic
design, less code, high re-usability)
6) Contract programming and unittest environment(early bug
source detection)
7) Compile time reflections and code generation (generative testbenches)
8) ABI compatible with C/C++ (creates single executable with
C/C++)
9) Pointer-less and garbage collected (no need of memory management, higher productivity)
10) Fast and advanced constraint randomization (less simulation
time)
11) Multicore enabled, word to word translated UVM-1.1d (ref
Section II)
II. M ULTICORE UVM I MPLEMENTATION IN V LANG
Vlang enables multicore parallelism in its UVM port (ref Figure 3).
Vlang UVM classifies the testbench components into the following
categories:
uvm_test
uvm phase
mechanism
uvm objection
mechanism
shared testbench
components
uvm config
object
uvm_component
scoreboard
uvm_agent
shared objects
coverage
uvm_env
Design Under Verification (DUV)
Fig. 3.
Multicore Enabled Vlang UVM Architecture
A. UVM Agents
An agent in UVM provides the right abstraction for reuse. The
software analogy for a uvm_agent is a package. There is very little
(and controlled as we see in the next section) interaction across the
various UVM agents in a testbench. And therefor, for multicore considerations too, UVM agent provides the right context for parallelism.
In Vlang, the various UVM agents are all executed independently
on multiple cores. A verification infrastructure architect retains the
flexibility to make any higher or lower level UVM component a
parallelization context.
B. Shared Objects
All the interaction between the various UVM agents is limited
to shared objects like the Objection Mechanism, UVM Phases and
Configuration Database. Fortunately, all these shared objects are
singletons and are instantiated inside the UVM library. Vlang port of
UVM puts the synchronization controls for all these shared objects to
make sure that there are no race conditions in a multicore testbench.
C. Shared Testbench Components
Some testbench components like the scoreboard might actively
interface with multiple UVM agents. But all such interaction happens
via UVM TLM ports/exports. Vlang UVM has synchronization
controls in place in the TLM port/export implementation to help avoid
any possible race conditions.
III. V LANG D EMONSTRATION E XAMPLES
1) A multicore enabled testbench based on a multicore implementation of UVM in Vlang.
2) SystemC Co-Simulation with Vlang with a demonstration of
shared data operations between SystemC and Vlang.
3) Verilog Co-Simulation with Vlang using DPI to interact between the testbench and the design.
4) Constraint solving and Randomization capabilities of Vlang.
Demonstration of multicore enabled constraint solvers and
randomization stability in multicore environments.
5) By far the fastest compilation and incremental compilation of
testbenches in comparison to other verification languages.
6) Utilization of metaprogramming and generative programming
features in Vlang to make cleaner and more succinct UVM
testbenches.
IV. C ONCLUSION
Vlang is an opensource verification language with many possibilities and solutions for the next generation. It is built on top of
D programming language, which comes with strong library support.
While today Vlang implements a port of UVM, the language capabilities provide it a potential for implementing far more powerful
verification libraries and methodologies in future.
R EFERENCES
[1] P. Goel and S. Adhikari, “Introduction to Next Generation Verification
Language - Vlang,” in Design and Verification Conference & Exhibition
Europe, To be published. DVCon Europe 2014, 2014, pp. 1–8.
[2] A. Alexandrescu, The D programming language.
Addison-Wesley
Professional, 2010.
[3] D. C. Black, J. Donovan, B. Bunton, and A. Keist, SystemC: From the
ground up. Springer, 2004.
[4] C. Spear, SystemVerilog for Verification. Springer, 2006.
[5] P. Goel, A. Sharma, and H. V. Balisetty, “C you on the faster side: Accelerating sv dpi based co-simulation,” Proceedings of Design Verification
Conference, San Jose, 2014.
[6] B. Bailey and G. Martin, ESL Models and their Application: Electronic
System Level Design and Verification in Practice. Springer, 2010.

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