Standard cell analysis and Modulo

ELEC 5250_6250 Project 7
Due: Tuesday, October 28, 2014
For this assignment, a project report is to be submitted electronically as a Word or PDF document.
We will be using the 2008 “icflow” design tools and ASIC Design Kit (ADK) for the remaining
projects. The appropriate path names are defined in the sample “.bashrc” file posted on the class
web page.
OPTIONAL ACTIVITY (In lieu of having classes on Oct. 21 and 23.)
Santa Clara University has web site containing several tutorials for design with Mentor Graphics
Tools: http://www.dc.engr.scu.edu/mentortu/index.html. The example under “Custom IC Design –
Digital” takes you through the process of creating an inverter, beginning with entering a transistor
schematic through the final layout. You might consider going through this tutorial to create your
own inverter circuit, as a way of becoming more familiar with the schematic entry, simulation, and
layout tools.
ASSIGNMENT PART A
Open IC Station (using the “adk_ic” script). In the palette, click “Open” under “Cells”. Navigate to
the $ADK directory, and open the layout cell “ee6260” (this is an “unknown standard cell” layout).
You are to determine the digital circuit implemented by this layout (2-input NAND gate? D flipflop?, etc.) Study this cell, sketch a transistor schematic diagram, and identify the digital circuit that
this implements.
1. Identify the transistors in the layout.
2. Identify the interconnections between the transistor terminals, including connections to
power and ground wires, and cell inputs/outputs. (Note that interconnections are formed
with polysilicon (red), metal 1 (blue), and metal 2 (purple).
3. Clicking on any object will select it and display information about the object in the status
window at the bottom of the screen.
4. Draw the transistor schematic diagram in Design Architect-IC (open with the script
adk_daic), and put a screen capture of the diagram into your project report and indicate the
type of digital component this implements.
ASSIGNMENT PART B
ELEC 5250 students may do only the modulo-5 counter in steps 1 and 2; the divider may be done for
extra credit in these steps.
1. Use LeonardoSpectrum to resynthesize both your modulo-5 counter and divider circuits in the
TSMC 0.35um (tsmc035) technology.
a. You should generate both VHDL and Verilog netlists and an SDF file.
b. Compare the area reports for the gdk and tsmc035 netlists and discuss any differences
in the synthesized circuits.
c. Compare the critical paths in the gdk and tsmc035 netlists and discuss any differences in
the synthesized circuits. What are the maximum clock frequencies for the counter and
the divider for each technology?
2. Perform simulations of the synthesized counter and divider netlists for the tsmc035 technology.
a. Verify that the circuits perform the correct functions.
b. Measure and compare the critical path delay to that reported by Leonardo.
Note that you will need to create a new library in Modelsim of the ADK standard cells, similar to
the one you created earlier for the GDK standard cells. The required VITAL models of the cells
are in directory $ADK/technology: adk.vhd and adk_comp.vhd.
3. Import the synthesized counter Verilog netlist (tsmc035 technology) into Design Architect-IC.
Put a “screen capture” of the schematic diagram from Design Architect-IC, into your project
report.
4. Generate the design viewpoints needed for IC Station and Calibre (use the adk_dve script).
5. Create a layout of your circuit in IC Station, using the automated place and route features of the
tool. Put a screen capture of the final layout into your project report.
6. Run the design rule checker (ICrules) and note the number of design rule violations, if any. For
each design rule violation:
a. Show the violation on the layout (zoom in as necessary) and put a screen capture into
your project report.
b. Discuss why this is a violation, and what should be done to correct it.
c. Optionally – correct the violation and put a screen capture of the correction into your
project report. (Ideally, you should end up with 0 violations.)
7. Read each of the report files created by IC Station. For each of these, write a sentence in your
project report, discussing one “interesting thing” you found in the IC Station report.

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