Assignment

ECE 270
Introduction to Digital System Design
Spring 2015
Traditional Lecture Homework Set for Module 4
E-mail: __ __ __ __ __ __ __ __ @purdue.edu Class No: __ __ __ __ - __
Lab Div: ____
Your Class No. is the last four digits of your PUID followed by the first character of your last name.
This homework set will be graded for completeness during Experiment 13. Printed copies of these
pages along with your original (hand-annotated, not photocopied) written solution in the space
provided (unless otherwise indicated) are required in order to receive credit. Your completed homework
sheets must be included in your Lab Notebook at the time they are collected for evaluation. Failure to
follow these “rules” will result in a score of zero. NOTE: The purpose of homework is to provide an
opportunity for practicing the kinds of problems you will be asked to solve on quizzes and exams –
copying the work of someone else does not accomplish this.
1. Starting with the signed (two’s complement) binary number (1000 0000)2, perform eight consecutive
arithmetic right shifts and determine the signed base 10 result after each shift.
Arithmetic Right Shifts Binary Pattern Base 10 Equivalent
(initial value)
1000 0000
-128
1
2
3
4
5
6
7
8
2. Starting with the unsigned binary number (0000 0001)2, perform eight consecutive arithmetic left
shifts and write the unsigned base 10 result after each shift.
Arithmetic Left Shifts Binary Pattern Base 10 Equivalent
(initial value)
0000 0001
1
1
2
3
4
5
6
7
8
1
ECE 270
Introduction to Digital System Design
Spring 2015
3. Write down the role (purpose) and control signals (names and definitions) used by each of the simple
computer functional blocks (incorporating the advanced extensions).
• program counter
• role/purpose:
• control signals:
• memory
• role/purpose:
• control signals:
• instruction register
• role/purpose:
• control signals:
• arithmetic logic unit
• role/purpose:
• control signals:
• instruction decoder and microsequencer
• role/purpose:
• control signals:
• stack pointer
• role/purpose:
• control signals:
2
ECE 270
Introduction to Digital System Design
Spring 2015
4. Write an ABEL program that realizes bit i of the ALU block diagram illustrated below. All the
declarations required are provided.
DECLARATIONS
CLOCK pin;
AOE,ALE,ALX,ALY pin;
Cin pin; " carry in (shown as Ci-1)
DBi pin istype 'reg_d,buffer'; " data bus pin
Si node istype 'com'; " full adder sum output
Ci node istype 'com'; " full adder carry output
Xmux node istype 'com'; " full adder Xin multiplexer
Ymux node istype 'com'; " full adder Yin multiplexer
EQUATIONS
3
ECE 270
Introduction to Digital System Design
Spring 2015
5. Write an ABEL program that realizes a magnitude comparator which produces five output signals
(XEQY, XLTY, XLEY, XGEY, and XGTY) based on the difference between two 4-bit signed
numbers: X3X2X1X0 and Y3Y2Y1Y0. All the declarations required are provided.
DECLARATIONS
S3..S0 node istype 'com'; " sum functions
C3..C0 node istype 'com'; " carry functions
G3..G0 node istype 'com'; " generate functions
P3..P0 node istype 'com'; " propagate functions
X3..X0 node istype 'com'; " X operand
Y3..Y0 node istype 'com'; " Y operand
CIN node istype 'com'; " LSB carry-in
CF,NF,ZF,VF node istype 'com'; " condition codes
XEQY, XLTY, XLEY, XGEY, XGTY node istype 'com'; " comparator outputs
EQUATIONS
4
ECE 270
Introduction to Digital System Design
Spring 2015
6. Write an ABEL program that realizes a complete BCD “full adder cell” (the description of which
appears on pp. 10-11 of the Module 4 Lecture Summary notes). All the declarations required are
provided.
DECLARATIONS
X3..X0 node istype 'com'; " BCD operand X
Y3..Y0 node istype 'com'; " BCD operand Y
CIN node istype 'com'; " carry-in
S3..S0 node istype 'com'; " BCD sum digit (one’s position)
COUT node istype 'com'; " carry-out (ten’s position, also correction function)
Z4..Z0 node istype 'com'; " intermediate sum
EQUATIONS
5
ECE 270
Introduction to Digital System Design
Spring 2015
7. Modify the section of the IDMS source file, below, to provide up to 7 execute cycles (in addition to
a single fetch cycle). The original ABEL file is given in Tables 2-18 and 2-19 of the Supplemental
Text.
MODULE idmsr
TITLE 'IDMS with 7 Execution States'
DECLARATIONS
" State counter
SQA node istype 'reg_D,buffer'; " low bit of state counter
SQB node istype 'reg_D,buffer';
SQC node istype 'reg_D,buffer'; " high bit of state counter
" Synchronous state counter reset
RST node istype 'com';
" RUN/HLT state
RUN node istype 'reg_D,buffer';
" Decoded state definitions
S0 =
S1 =
S2 =
S3 =
S4 =
S5 =
S6 =
S7 =
EQUATIONS
" State counter
" If RUN negated or RST asserted, state counter is reset
SQA.d =
SQB.d =
SQC.d =
6
ECE 270
Introduction to Digital System Design
Spring 2015
8. Modify the ALU as shown in the function table so that CF and VF condition code bits are cleared by
the LDA and AND instructions (instead of being unaffected). Write the “new” equations for CF.d
and VF.d using ABEL syntax.
AOE
ALE
ALX
ALY
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
d
d
0
1
0
1
d
d
Function Performed
LDA: [Q3..Q0] ← [D3..D0]
AND: [Q3..Q0] ← [Q3..Q0] ∩ [D3..D0]
SUB: [Q3..Q0] ← [Q3..Q0] – [D3..D0]
ADD: [Q3..Q0] ← [Q3..Q0] + [D3..D0]
OUT: [D3..D0] ← [Q3..Q0]
(no operation – retain state)
CF
ZF
NF
0
0
-
VF
0
0
-
-
-
New equation for CF.d = _____________________________________________________
New equation for VF.d = _____________________________________________________
7
ECE 270
Introduction to Digital System Design
Spring 2015
RST
SPA
SPD
SPI
PLD
POD
PLA
H
ALY
H
ALX
H
ALE
H
AOE
H
IRA
H
IRL
H
POA

PCC
S0
MWE
Mnemonic
MOE
State
MSL
9. Identify the instruction mnemonic associated with each execute state (noting that some of the
instructions require two execute states). Choices include the following: ADD, SUB, LDA, STA, PSH,
POP, PPA (pop and add to accumulator), PPS (pop and subtract from accumulator), JSR, RTS, and
HLT. Assume the stack pointer points to the next available location.
S1
S1
H
S1
H
H
H
H
H
H
H
H
S1
H
S1
H
S1
H
H
H
S1
H
H
H
H
H
H
H
S2
H
H
H
S2
H
H
H
S2
H
H
H
H
Asynchronous Machine Reset
MSL
Memory Select
MOE
Memory Output Tri-State Enable
MWE
Memory Write Enable
PCC
Program Counter Count Enable
POA
Program Counter Output on Address Bus Tri-State Enable
PLA
Program Counter Load from Address Bus Enable
POD
Program Counter Output on Data Bus Tri-State Enable
PLD
Program Counter Load from Data Bus Enable
IRL
Instruction Register Load Enable
IRA
Instruction Register Output on Address Bus Tri-State Enable
AOE
A-register Output on Data Bus Tri-State Enable
ALE
ALU Function Enable
ALX
ALU Function Select Line “X”
ALY
ALU Function Select Line “Y”
SPI
Stack Pointer Increment
SPD
Stack Pointer Decrement
SPA
Stack Pointer Output on Address Bus Tri-State Enable
RST
RUN
Synchronous State Counter Reset
Machine Run Enable
H
H
H
H
H
AOE
ALE
ALX
ALY
0
0
0
1
0
1
1
1
0
0
0
0
1
d
d
0
1
0
d
d
H
Function
Add
Subtract
Load
Output
<none>
Instruction Decoder
and Micro-Sequencer
Opcode Address
Instruction
Register
Flags
ALU
Data Bus
CF
ZF
NF
VF
•
•
•
•
•
•
•
•
•
•
Program
Counter
Clock
Start
SP
Memory
Data
Description
START
H
H
Address
H
Data
S2
H
Address Bus
S1
Name
H
8

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