Experiment VERI: FPGA and Verilog Department of EEE Imperial College London Department of Electrical & Electronic Engineering Imperial College London 2nd Year Laboratory Experiment: FPGA Design with Verilog Objectives By the end of this experiment, you should know: • • • • • • How to design digital circuits using Altera’s Quartus II Design Suite; How to design digital circuits targeting Altera’s Cyclone III FPGA using a Terasic’s DE0 Board; How to design digital circuits in efficient Verilog HDL; How to evaluate your design in terms of resource utilization and clock speed; How to use DE0 FPGA board with its custom daughter board for I/O functions such as ADC and DAC; Have designed something yourself for the Cyclone III FPGA. Before you start You have been provided with the Headstart document and a DE0 Board. Before you come to the laboratory, you are expected to have: • • • Understood the lectures on Verilog Family with the basic architecture inside the FPGA Gone through the steps outlined in the Headstart document Both the experimental board and a PC would be made available to you during your allotted period in the second year laboratory. In addition, you may also borrow a DE0 board to take home to use for the rest of the second year. This instruction sheet is divided into four parts, one for each week. It also provides you with information required to install Altera’s Quartus II Design Suite (web free-‐version) on your own personal computer (PC or Mac). V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 1 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London PART I This is a repetition to the Headstart exercise. It is included here in case you did not have a chance to complete this before attending the laboratory session, or you faced difficulties. The goal of the exercise is to get you to learn how to use Quartus II, and to produce the schematic design of the 7-‐segment decoder circuit. If you have completed the Headstart exercise, please jump to step 11 directly. Experiment 1: Schematic capture using Quartus II – 7-‐Segment Display Part I of the experiment should take no more than ONE 3-‐hour session. It will lead you through the entire design of a 7-‐segment decoder using schematic entry method. It will use switches 3-‐0 on the DE0 board as input, and display the 4-‐bit binary number as a hexadecimal digit on the right-‐most 7-‐segment display (HEX0). Step 1: See what you are aiming for Go to the Experiment webpage (see above) and download a copy of the solution for Experiment 1: “My7Seg.sof” onto your home directory (wherever that is). Now turn ON the DE0 board. Step 2: Programme the FPGA Start up Quartus II software on your computer. Click command: Tools > Programmer. In the popup window, click: Hardware Setup …. You should see something like the diagram below. Then select: USB-‐Blaster. This is to tell Quartus software that you are using the DE0 USB interface to program (or blast) the FPGA. Then click Add File …. specify the .sof file you have downloaded from your home directory. Click: Start. This shows you what you are aiming for: use the lower 4-‐bit of the slide switches to specify a 4-‐bit hex number, which is decoded to drive a 7-‐segment LED display. Step 3: Paper Design Designed a 7-‐segment decoder on paper. The overall block diagram for the decoder is shown below. The decoder outputs out[6..0] drive the seven segments [6..0] respectively. Note that the LED segments are low active, meaning that the LED will light up if the corresponding input is drive by a logical 0. V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 2 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London The truth-‐table for the decoder is: Your design should be in the form of 7 Boolean equations in sum-‐of-‐product form. Simplify where possible. Step 4: Create the project “My7Seg” • • • • • • Create in your home directory the folder Ex1a. Click file>New Project Wizard, complete the form. Use the same project name and top-‐design name. Select the FPGA device as Cyclone III EP3C16F484C6. Then click Finish. Create the top-‐level module “My7Seg” by: Click File > New ….. There will be an empty schematic window. Click File > Save As… enter the name “My7Seg”. Step 5: Specify the 7-‐segment decoder as schematic • Download from the website the file: My7Seg.bdf.zip and unzip. This is a partially completed schematic for the 7-‐segment decoder circuit with one output (out[4]) missing. You are now ready to enter the circuit to produce out[4] as gates through the schematic editor. This is shown on the right and it implements the equation: out4 = /in3*in0 + /in3*in2*/in1 + /in2*/in1*in0 The Graphic Editor provides a number of libraries which include circuit elements that can be imported into a schematic. Double-‐click on the blank space in the Graphic Editor window, or click on the icon in the toolbar that looks like an AND gate. A pop-‐up box will appear. Expand the hierarchy in the Libraries box as shown in the figure. First expand libraries, then expand the library primitives, followed by expanding the library logic which comprises the logic gates. Select “and2”, which is a two-‐input AND gate, and click OK. Now, the AND symbol will appear in the Graphic Editor window. Using the mouse, move the symbol to a desirable location and click to place it there. • Repeat and place two “and3” and one “or3” gates on the schematic. Change the names of all the input and output nodes accordingly. (It is quickest to put down all the gates first before wiring them up later.) V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 3 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London • Having entered the logic-‐gate symbols, it is now necessary to enter the symbols that represent the input and output ports of the circuit. Use the same procedure as for importing the gates, but choose the port symbols from the library primitives/pin. Import one instance of the input port and one instance of the output port. Label the input port as in[3:0] and output port as out[6:0]. Grouping input and output ports as busses will make wiring much easier. • Assign names to the input and output symbols as follows. Make sure nothing is selected by clicking on an empty spot in the Graphic Editor window. Point to the word pin_name on the top input symbol and double-‐click the mouse. The dialog box will appear. Type the pin name, in[0], and click OK. Similarly, assign the names in[3..1] to the other input ports and out[4] to the output port. Alternatively, it is possible to change the name of an element by selecting it first, and then double-‐ clicking on the name and typing a new one directly. • You are now ready to wire up the gates. Click on the icon in the toolbar to activate the Orthogonal Node Tool. Position the mouse pointer over the right edge of the input pin. Click and hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub of the gate. Release the mouse button, which leaves the line connecting the two pinstubs. Note that a dot will appear indicating a connection between the two wires. All nodes with the same name will be connected. • Having completed the circuit for out[4], you now need to do the same for the other six outputs. Step 6: Include this file in project Every time you create a new entity or module as part of your design, you must include the file in the project. • Click: Project > Add Current Files to Project …., Step 7: Make a symbol for the decoder It is often convenient to encapsulate a circuit into a module, which is then used multiple times in a design. This is called an “entity”. For us to do so, we need to create a symbol for it. (This will create a 7_Segment_Decoder.bsf file.) Click File > Creat/Update > Create Symbol … Step 8: Use this module at the top-‐level design schematic • Open “My7Seg”, the empty top-‐level design entry file. • Use the button to place the 7_Segment_Decoder module, input port and output port on the schematic. • Double click the port symbol to edit the Pin Property, and enter the input and output names as SW[3..0] and HEX0_D[6..0] respectively. V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 4 Experiment VERI: FPGA and Verilog • • Use the bus wiring tool shown below. Save this file. Department of EEE Imperial College London to wire up the ports to the module as two busses as Step 9: Pin assignment & Compilation You need to associate your design with the physical pins of the Cyclone III FPGA on the DE0 board. • • • • First specify the device by clicking: Assignments > Device … Select Cyclone III EP3C16F484C6 (check that this is indeed the chip on the DE0 board). Click: Processing > Start > Start Analysis and Elaboration. This will work out the input/output port names for your design. This should complete without error. Otherwise, fix all errors and re-‐analyse. Click Assignment > Pin Planner and a new window with the chip package diagram. You should also see the top-‐level input/output ports shown as a list. V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 5 Experiment VERI: FPGA and Verilog • • Department of EEE Imperial College London Click on the appropriate pins one by one, and select the corresponding port (node name) according to the list shown below. The I/O standard (i.e. interface voltages) should be “3.3V LVTTL”. Click: Processing > Start Compilation, to build the entire design, and to generate all the necessary files. There should be NO error, but some warnings. Step 10: Program the FPGA on the DE0 Board • Program the DE0 board with your version of My7seg.sof and test that it is working properly. Congratulations! You have now completed your first FPGA design! JUMP HERE IF YOU HAVE COMPLETED THE HEADSTART EXERCISE AT HOME. Exercise 1 -‐ Continued: Exploring the hardware on the FPGA This is to be continued from the previous part of the experiment. Step 11: Propagation Delay from inputs to outputs • • • • • • • Click: Tools > TimeQuest Timing Analyzer to invoke the built in timing analyzer of Quartus II. A new TimeQuest window will appear. Click: Netlist > Create Timing Netlist. Then select post-‐fit and slow-‐corner, then OK. Now click: Netlist > Set Operating Conditions … Then choose the slow model at 0°. Now click: Netlist > Update Timing Netlist … This will use the specified timing model and condition to produce a set of timing data. Click: Report > Datasheet > Report Datasheet. This will produce a table showing the input-‐to-‐output propagation delay for various combination of rise and fall times (RR, RF, FR and FF). Explore this to find out the worst-‐case propagation delay for your circuit. Then delete this timing netlist, and redo it again choosing 85°C as the operating temperature. What is the delay difference at these two temperature extremes? Step 12: Examine the resources used • • • • We now examine how Quartus has compiled your specification (from schematic) to actual FPGA hardware. In the Compilation Report window, you should have seen that your design used 7 logic elements. Let us make sure that the FPGA implementation of out[4] is identical to your specification. Click: Tools > Netlist Viewers > Technology Map Viewer (Post-‐fitting). Then push down into the 7_Segment_Decorder module. You should see 7 instances of the logic element. Identify which Logic Element (LE) provides out[4]. Hover the mouse pointer to this LE (corresponding to out[4]), you should see a pop-‐up window with the Boolean equation of the FPGA implementation. (Note that in Quartus, & = AND, # = OR, $ = XOR, ! = NOT.) V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 6 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London • Right click the symbol and select properties in the pop-‐up window. You will see the schematic equivalent of the Boolean equation: • Check that this performs the same logic function as that specified in your schematic out[4]. (Don’t trace for any other outputs.) In general, you do not need to worry about exactly how Quartus implements your logic. The synthesis software should provide a design that exactly matches your specification. Experiment 2: 7-‐Segment decoder in Verilog HDL I hope you now appreciate how limiting and slow it is to enter a design as a schematic diagram. Modern digital designs DO NOT USE schematic as a method of entry any more. Instead a designer would either use Verilog or VHDL hardware description language to specify the design. By the end of this laboratory session, you should be convinced about the superiority of using a HDL over schematic capture. Step 1: hex_to_7seg.v • • • Create a new project Ex2a as before, with a top-‐level schematic module as before. You may call it Ex2a_Decoder. In Quartus II, create a design file in Verilog HDL known as hex_to_7seg.v. The actual code is given to you in Lecture 3A slide 18 and is repeated here. A full compilation can take a long time. A far more efficient way to check the syntax of your code by clicking: Process > Analyze current file. After you verify that the current file has no syntax error. Then you must check that it is consistent with other files in your design by clicking: Process > Start > Start analysis & elaboration. Make sure that there are no error, and if there are warnings, make sure that these are either dealt with or understood. Warnings often capture potential errors. You will save a lot of time if you ALWAYS use these two steps, and ensure that ALL errors and warnings are dealt with (or understood). V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 7 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London Step 2: Create a SYMBOL for this Verilog module • Click: File > Create/Update > Create Symbol file …. Step 3: Create the top-‐level schematic file • • • • Similar to last exercise, insert the symbol for the module hex_to_7seg in your new schematic file “Ex2a_Decoder.bdf”. Add input ports SW[3..0] and output ports HEX0_D[6..0], and connect to your decoder module. Beware of the difference in Quartus’ method in specifying a bus. It uses SW[3..0], which is different from Verilog using SW[3:0]. Compile the whole design. You should find that this design works as before. Step 4: Pin Assignment – the quick way • • • Earlier you used the pin assignment editor to associate pins on the package to your signals. This is a tedious process. In Ex1, if you have correctly completed the design, the pin assignment would have been stored in a file: “My7Seg.qsf” file. Open this file, either using Quartus’ built-‐in editor by clicking: File > Open file… or use your own favourite edit on your PC. You will find lines of statement such as: • • • The first line defines the voltage standard used by the SW[3] signal. The second line defines the pin location of SW[3] is PIN G4. Now open the .qsf file for your current design, and copy & paste the assignments from Ex1 across. You will find that this is the easiest way to deal with PIN assignment with minimal chance of introducing an error. Step 5: Test your design • • Recompile your design, load your configuration to the DE0 board using: Tool > Programmer command. Test your design on the DE0 board. V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 8 Experiment VERI: FPGA and Verilog Department of EEE Imperial College London Step 6: Do everything in Verilog – including Top-‐Level Specification • • • • • It is in fact much easier to eliminate all needs for schematic capture. You can replace the top level schematic file “Ex2a_Decoder.bdf” with “Ex2a_Decoder.v”. Create this top level Verilog file as shown here. Click: Project > Add/Remove Files, and remove the .bdf file as part of this project. This allows you to remove the .bdf file and replace it with the .v file for the top-‐level specification. Compile and test. Step 7: Do this yourself Now complete this exercise but including the remaining switches and three of the four 7-‐segment LED display. You should find that doing so is much easier in Verilog than using schematics. You can find the pin assignment given in the file “pin_assignment.txt” (downloadable from the experiment webpage). Adding this to the .qsf file using a text editor is much easier than editing each pin one at a time. Checkpoint: You should get to this point by the end of the first week. Pin Assignments for the 4 HEX displays and 13 switches on DE0 board V3.1 -‐ PYK Cheung, 16 Nov 2014 Part 1 -‐ 9
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