Lab manual for ES23 - Sonoma State University

ELECTRONICS I LABORATORY
MANUAL
Spring, 2014
Jack Ou
Engineering Science
Sonoma State University
A SONOMA STATE UNIVERSITY PUBLICATION
CONTENTS
1
Linux Tutorial
1
1.1
1.2
1
1
1
2
2
3
3
4
4
5
1.3
2
Login to Redhat
Basic Stuffs
1.2.1
Finding Your Way with pwd
1.2.2
Listing Directories and Files with ls
1.2.3
Changing Directories with cd
1.2.4
Creating Directories with mkdir
1.2.5
Removing Directories with rmdir
1.2.6
To copy a file
1.2.7
Removing a file
Starting Cadence
Circuit Simulation Using Virtuoso
2.1
2.2
2.3
2.4
Objectives
Before You Start
Insert a Diode In the Schematic
Analog Design Environment
7
7
7
8
14
iii
iv
CONTENTS
2.5
3
4
5
6
7
Submission Checklist
15
I-V Characteristic Curve of a Diode
17
3.1
3.2
3.3
3.4
3.5
3.6
17
17
17
18
19
19
Objectives
References
Parts
Forward Biased Diode
Reverse Bias Diode
Submission Checklist
Diode Logic
21
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
21
21
21
22
22
22
23
25
References
Objectives
Parts
Assumptions
A 2-input OR gate
A 2-input AND gate
A 3-input OR2-AND2 gate
Submission Checklist
Bipolar Junction Transistors
27
5.1
5.2
5.3
5.4
5.5
5.6
27
27
28
28
29
31
Objectives
Parts
Testing a Transistor with a DMM
Determine Terminals of a BJT
The BJT Characteristic Curve
Submission Checklist
NAND Gate
33
6.1
6.2
6.3
6.4
6.5
6.6
33
33
34
35
36
36
References
Objectives
Analysis
Design and Simulation
Hardware Implementation
Submission Checklist
DC Operating Point of an FM Wireless Microphone Circuit
37
7.1
37
References
CONTENTS
7.2
7.3
7.4
7.5
8
9
37
38
38
39
40
40
41
41
Small Signal Analysis of an FM Wireless Microphone Circuit
43
8.1
8.2
8.3
8.4
8.5
8.6
8.7
References
Objectives
Data from last week
Analysis
Simulation
Measurement
Submission Checklist
43
43
44
44
45
45
45
One-Transistor FM Transmitter
47
9.1
9.2
9.3
47
47
48
48
48
49
9.4
10
Objectives
Analysis
7.3.1
Constants and Equations
7.3.2
DC operating point analysis of the audio amplifier
7.3.3
DC operating point analysis of the RF oscillator
7.3.4
DC operating point analysis of the RF amplifier
Simulation
Submission Checklist
v
References
Objectives
Preliminary Calculation
9.3.1
Coil Inductor
9.3.2
Base-Collector Capacitance
Measurement
Application of MOS transistors in Digital Circuits
51
10.1
10.2
10.3
51
51
52
52
52
53
53
53
54
54
54
10.4
10.5
References
Objectives
Resistively loaded NMOS Inverter
10.3.1 Analysis and Simulation
10.3.2 Measurement
Resistively loaded PMOS
10.4.1 Analysis and Simulation
10.4.2 Measurement
CMOS Inverter
10.5.1 Analysis
10.5.2 Simulation
vi
CONTENTS
10.6
10.5.3 Measurement
A Two-Input CMOS Logic Gate
54
55
CHAPTER 1
LINUX TUTORIAL
1.1
Login to Redhat
Start the machine in the Redhat environment with the following user name and password:
User: r2d2
Password: student
1.2
1.2.1
Basic Stuffs
Finding Your Way with pwd
pwd displays the path and name of the directory you are currently in, giving you the
full picture of where you are. (Right Click ⇒ Open Terminal)
[r2d2@localhost ˜]$ pwd
/home/r2d2
Electronics I Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 1
2
1.2.2
LINUX TUTORIAL
Listing Directories and Files with ls
Your Linux system is made up of directories and files that store a variety of information. Using the ls, you can find out exactly what is in your Linux system and
thereby find out what is available to you. You can list the files and directories of a
directory you are currently in.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$
1.2.3
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
Changing Directories with cd
To explore Linux and its capabilities, you’ll need to move around among the directories. You do so using the cd command, which takes you from the directory you
are currently in to one that you specify. To move to a specific directory, type cd plus
the name of the directory. In the example below, we move down in the directory to a
subdirectory called design.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ cd design
[r2d2@localhost design]$ pwd
/home/r2d2/class
[r2d2@localhost design]$
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
BASIC STUFFS
3
Type cd .. to move up one level.
[r2d2@localhost class]$ pwd
/home/r2d2/design
[r2d2@localhost design]$ cd ..
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$
1.2.4
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
Creating Directories with mkdir
You might think of directories as being drawers in a file cabinet; each drawer contains
a bunch of files that are somehow related. For example, you might have a couple
of file drawers for your unread magazines, one for your to-do lists, and maybe a
drawer for your work projects. Similarly, directories in your Linux system act as
containers for other directories and files. You create new directories using the mkdir
command.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ mkdir drawer
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME drawer
cadence
class
instruct
cdb2oa.log
design
libManager.log
CDS.log
Desktop
linux.tutorial.text
CDS.log.1
download
mentor
[r2d2@localhost ˜]$ cd drawer
[r2d2@localhost drawer]$ pwd
/home/r2d2/drawer
[r2d2@localhost drawer]$
1.2.5
Removing Directories with rmdir
You can remove a directory using rm -r followed by the directory name.
[r2d2@localhost ˜]$ pwd
mgc
models
panic.log
share
simulation
start
store
4
LINUX TUTORIAL
/home/r2d2
[r2d2@localhost ˜]$ mkdir drawer
[r2d2@localhost ˜]$ cd drawer/
[r2d2@localhost drawer]$ pwd
/home/r2d2/drawer
[r2d2@localhost drawer]$ cd ..
[r2d2@localhost ˜]$ rm -r drawer
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME instruct
cadence
class
libManager.log
cdb2oa.log
design
linux.tutorial.text
CDS.log
Desktop
mentor
CDS.log.1
download
mgc
[r2d2@localhost ˜]$
1.2.6
models
panic.log
share
simulation
start
store
instruct
libManager.log
linux.tutorial.text
mentor
mgc
CDS.log.bak
models
panic.log
share
simulation
start
store
download
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
mgc
start
To copy a file
You can copy a file by using the following syntax.
cp existingfile new file
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ cp CDS.log
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.bak
cadence
CDS.log.CDSHOME
cdb2oa.log
class
CDS.log
design
CDS.log.1
Desktop
[r2d2@localhost ˜]$
1.2.7
Removing a file
Use rm followed by the name of the file to be deleted.
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.bak
download
STARTING CADENCE
cadence
CDS.log.CDSHOME instruct
cdb2oa.log
class
libManager.log
CDS.log
design
linux.tutorial.text
CDS.log.1
Desktop
mentor
[r2d2@localhost ˜]$ rm CDS.log.bak
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME instruct
cadence
class
libManager.log
cdb2oa.log
design
linux.tutorial.text
CDS.log
Desktop
mentor
CDS.log.1
download
mgc
[r2d2@localhost ˜]$
1.3
5
models
panic.log
share
simulation
store
models
panic.log
share
simulation
start
store
Starting Cadence
1. Start a NEW terminal.(Right click → Open Terminal)
2. Go to the design directory.
3. Type rm -rf cmrf7sf.V1.9.0.2.ML to remove the existing start-up
directory.
4. Open the course webpage with a FireFox browser.
5. Download cmrf7sf.tar from the course website.
6. Type +tar -xvf cmrf7sf.tar+ to extract the tar file.
7. Go to the cmrf7sf.V1.9.0.2.ML directory.
8. Type virtuoso & at the command prompt to start Cadence.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ cd design
[r2d2@localhost design]$ pwd
/home/r2d2/design
[r2d2@localhost design]$ ls
AMSDesigner cmrf7sfML
envexp
AMSDInADE
cmrf7sf.V1.9.0.2.ML libConvert.txt
AnaSimTech
cmrf8sfDM
mentor
[r2d2@localhost design]$ cd cmrf7sf.V1.9.0.2.ML
[r2d2@localhost cmrf7sf.V1.9.0.2.ML]$ pwd
/home/r2d2/design/cmrf7sf.V1.9.0.2.ML
[r2d2@localhost cmrf7sf.V1.9.0.2.ML]$ virtuoso &
[1] 16648
spb16.5
tmpCphMsg
CHAPTER 2
CIRCUIT SIMULATION USING
VIRTUOSO
2.1
Objectives
After completing this lab, you will be able to
1. Create a schematic.
2. Place components in a schematic.
3. Include a model file.
4. Run a DC simulation.
2.2
Before You Start
1. Please review the materials covered in Chapter ?? before you continue.
2. Remember to start Virtuoso in the cmrf7sf.V1.9.0.2.ML directory. If
you start Virtuoso in any other directory, you will not be able to access the
user libraries, e.g. sandBoxML.
Electronics I Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 7
8
CIRCUIT SIMULATION USING VIRTUOSO
2.3
Insert a Diode In the Schematic
1. Start a new schematic. (File⇒New⇒Cellview)
2. Set the library, cell and view to the followings and press OK. (e.g. Figure 2.1)
(a) Library: sandBoxML
(b) Cell: diode_tst
(c) View: schematic
sandBoxML will be the default user library for this course. If you look under
the library pull-down menu, you will see other libraries such as analogLib
and basic. Please do not create any new schematic in analogLib. analogLib
is a standard library that provides commonly used components such as resistors,
capacitors..etc. We want to avoid making any changes to this library.
Figure 2.1: Create a new schematic.
INSERT A DIODE IN THE SCHEMATIC
9
3. Use Create ⇒ Instance to add a diode to the schematic. You can also activate
the same feature by pressing i with the mouse pointer in the schematic window.
Set the fields to the following values: (Figure 2.2)
(a) Library: analogLib
(b) Cell: diode
(c) Model name: 1n4001. This is the part number of the diode. You do not
need to specify the path of the model file in this window. The path is specified in the Analog Design Environment. A common mistake is to use the
model file name 1n4001.m for the model name.
Figure 2.2: Add a diode to the schematic.
There are other features such as Sotate, Sideways, and Upside Down in
the Add Instance window. Please experiment with these features on your
own. You will find these features useful in later experiments. You can drop a
diode in the schematic with a left-click. You can escape from the add instance
mode at any time by pressing the Esc key. You can delete any component from
the schematic with the Delete key.
10
CIRCUIT SIMULATION USING VIRTUOSO
4. Use Create ⇒ Instance (or shortcut key i) to add a resistor to the schematic.
Set the fields to the following values: (e.g. Figure 2.3)
(a) Library: analogLib
(b) Cell: res
(c) Resistance: 1K Ohms.
You can move the resistor by selecting Edit ⇒ Move (or shortcut key m) and
dragging it with the mouse.
Figure 2.3: Add a resistor to the schematic.
INSERT A DIODE IN THE SCHEMATIC
11
5. Use Create ⇒ Instance, or shortcut key i, to add a DC voltage source to the
schematic. Set the fields to the following values: (e.g. Figure 2.4.)
(a) Library: analogLib
(b) Cell: vdc
(c) DC voltage: 1 V.
Figure 2.4: Add a voltage source.
12
CIRCUIT SIMULATION USING VIRTUOSO
6. Use Create ⇒ Instance to add the reference ground to the schematic. Set the
fields to the following values: (e.g. Figure 2.5)
(a) Library: analogLib
(b) Cell: gnd
Figure 2.5: Add the ground to the schematic.
INSERT A DIODE IN THE SCHEMATIC
13
7. Complete the circuit by using narrow wires to connect devices in the schematic.
(Create⇒Wire(narrow), or shortcut key w) You can use the Esc key to exit
from the wiring mode when you are done wiring the circuit. (e.g. Figure 2.6)
Note that the circuit in Figure 2.6 is off-center. You can activate the “Zoom to
Fit” feature by using the shortcut key f.
Figure 2.6: The complete Circuit
8. Click on Check and Save, which is identified by the red box in Figure 2.6.
The simulator will search for error(s) in the schematic when Check and Save
is selected. If you change the schematic without running a Check and Save
before executing the simulation, you will not be able to run the simulation. You
can usually catch this error by looking for the netlisting error shown in Figure 2.7. Cadence is very picky. Even if you move the resistor without actually
changing the value of the resistor, it will expect that you do a Check and Save
before runnning the simulation.
14
CIRCUIT SIMULATION USING VIRTUOSO
Figure 2.7: Netlist Error
2.4
Analog Design Environment
1. Start Analog Design Environment from your schematic. (hint: Launch ⇒ ADE
L) You may get a window similar to the one in Figure 2.8. Select Yes to
continue.
Figure 2.8: License Check Out
2. Use a browser to download the model file for the diode from the course website.
The model file you need is 1n4001.m. (1n4001 corresponds to the model name
we entered for the diode.) Save it to /home/r2d2/models/discrete
directory. You can also verify that the file has been saved to the right directory
as follows:
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ cd models/discrete/
[r2d2@localhost discrete]$ pwd
/home/r2d2/models/discrete
[r2d2@localhost discrete]$ ls
1n4001.m 2n3904.m 2n3906.m npn.scs qtyp.m.bak
[r2d2@localhost discrete]$
[r2d2@localhost discrete]$ pwd
/home/r2d2/models/discrete
[r2d2@localhost discrete]$
3. Setup ⇒ Model Libraries:
ua741.m
SUBMISSION CHECKLIST
15
(a) Make sure the path to the 1n4001.m is included. (Make sure paths to other
models are un-selected)
4. Select DC analysis. (ADE: Analysis ⇒ Choose)
(a) Choose dc for DC analysis.
(b) Check the box next to Save DC Operating Point.
(c) Select the box next to Enabled.
(d) Press OK.
5. Start Simulation. (ADE: Simulation ⇒ Netlist and Run.) You can also
Netslit and Run by selecting the green play button in ADE.
6. Annotate nodal voltages. (ADE: Results ⇒ Annotate ⇒ DC Node Voltages.)
7. The voltages should be displayed on the schematic. Read node voltages off
schematic.
8. What is the voltage across the diode?
2.5
Submission Checklist
1. Submit a hardcopy of DC-annotated schematic. You should be able to see
the voltage across the diode on the schematic. (2 points) You can use either the screen capture or the Export Image feature in the schematic editor window to export the image to the default Cadence start-up directory, i.e.
cmrf7sf.V1.9.0.2.ML directory.
CHAPTER 3
I-V CHARACTERISTIC CURVE OF A
DIODE
3.1
Objectives
1. Measure the I-V characteristic curve of a diode.
2. Plot the I-V characteristic curve of a diode.
3.2
References
1. Section 2.2-2.3, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
3.3
Parts
1. 1 1N914 diode
2. 1 100 Ω resistor
Electronics I Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 17
18
3.4
I-V CHARACTERISTIC CURVE OF A DIODE
Forward Biased Diode
+ V
− S
+ VR −
100Ω
+ ID
VD 1N 914
−
Figure 3.1: Forward Biased Diode.
1. Figure 3.1 is the schematic for measuring the I-V characteristic curve of a forward biased diode. VS is the voltage generated by the power supply. VR is the
voltage across the resistor. VD is the voltage across the diode. ID is the current
of the diode.
2. Applying KVL around the loop once, we get
VS = VR + VD
(3.1)
3. Recall that VR = ID R. We can re-write Eqn. (3.1) as follows:
VS = ID R + VD
(3.2)
4. We can solve for ID using Eqn. (3.2). R is 100 Ω in this experiment. VS and
VD can both be measured.
ID = (VS − VD )/R
(3.3)
5. Measure the I-V characteristic curve of the 1N914 diode by sweeping VS from
0.0 V to 1.5 V at 0.1 V intervals. Tabulate the results in a Table 3.1. You may
have to record the results on a separate sheet of paper.
VS
VD
ID
0.0V
1.5 V
Table 3.1: I-V characteristic curve of a diode
6. Plot the I-V characteristic curve using Excel. Please refer to the Excel tutorial
(available from the course website) if you need help plotting a scatter graph.
REVERSE BIAS DIODE
+ V
− S
+ VR −
100Ω
19
−
1N 914 VD
ID +
Figure 3.2: Reverse Biased Diode.
3.5
Reverse Bias Diode
1. Sweep VS from 0 V to 1.0 V at 0.5 V interval. Measure VD , the voltage across
the diode.
VS
VD
ID
0.0 V
0.5 V
1.0 V
Table 3.2: I-V characteristic measurement of a reverse biased diode.
3.6
Submission Checklist
The write-up for this lab is due in the beginning of the next lab.
1. Submit Table 3.1. (2 points)
2. Submit a plot of I-V using data from Table 3.1. (3 points)
3. Submit Table 3.2. (1 points)
4. Under the constant-voltage diode model, the exponential I-V characteristics of
the diode is modeled with a battery in series with an ideal switch. VD,on is the
value of the battery. (See Figure 2.33 in the textbook) What should be the value
of VD,on for 1N914 diode? (3 points)
5. Using Section 2.2.2 of the textbook as a guide, can you explain why the diode
carries so little current when it is reverse biased? (3 points)
6. Using Section 2.2.3 of the textbook as a reference, can you explain why the
diode is capable of carrying a significant amount of current under forward bias?
(3 points)
CHAPTER 4
DIODE LOGIC
4.1
References
1. Section 3.1, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
2. Chapter 1 and chapter 2 of the ES230 lab manual.
4.2
Objectives
After completing this lab, you will be able to
1. Build an OR gate using diodes.
2. Build an AND gate using diodes.
3. Implement a simple logic function using diode logic gates.
4.3
Parts
1. 4 1N914 diode
Electronics I Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 21
22
DIODE LOGIC
2. 1 1 KΩ resistor
4.4
Assumptions
Please assume the following values in this experiment.
1. VDD = 3 V
2. “1” = 3 V
3. “0” = 0 V
4.5
A 2-input OR gate
1. Figure 4.1 shows a 2-input OR gate implemented with two diodes and one resistor (ROR ). ROR is 1 KΩ in this circuit.
VA
VB
ROR
Vout
Figure 4.1: A 2-input OR gate implemented with diodes.
2. Simulate the circuit using Cadence. Record Vout,sim , the simulated output voltage, in Table 4.1.
3. Next, build the circuit on a breadboard and record Vout,meas , the measured
output voltage, in Table 4.1.
4.6
A 2-input AND gate
1. Figure 4.2 shows a 2-input AND gate implemented with two diodes and one
resistor (RAN D ). RAN D is 1 KΩ in this circuit. VDD is 3 V in this circuit.
A 3-INPUT OR2-AND2 GATE
VA (V)
VB (V)
0
0
0
3.0
3.0
0
3.0
3.0
Vout,sim (V )
23
Vout,meas (V )
Table 4.1: Truth table for the 2-input OR circuit.
VDD
RAN D
VB
Vout
VA
Figure 4.2: A 2-input AND gate implemented with diodes.
2. Simulate the circuit using Cadence. Record Vout,sim , the simulated output voltage, in Table 4.2.
3. Next, build the circuit on a breadboard and record Vout,meas , the measured
output voltage, in Table 4.2.
VA (V)
VB (V)
0
0
0
3.0
3.0
0
3.0
3.0
Vout,sim (V )
Vout,meas (V )
Table 4.2: Truth table for the 2-input AND circuit.
4.7
A 3-input OR2-AND2 gate
Finally, we build a circuit that implements F = AC + BC. We can implement F
with a 2-input OR and a 2-input AND by re-writing F as F = (A+B)C. The circuit
implementation of F is shown in Figure 4.3. Vout1 represents the output formed by
A + B and Vout2 represents the output of F . VDD is tied to a 3 V power supply in
this circuit.
24
DIODE LOGIC
VB
VA
VDD
D1
D2
ROR
Vout1
D3
RAN D
Vout2
VC
D4
Figure 4.3: A 3-input OR2-AND2 gate implemented with diodes.
1. We will start by using ROR and RAN D values used in the previous experiment,
i.e. ROR = RAN D = 1kΩ.
2. What is the simulated value of F when A = B = 0 and C = 1?
3. Simulate the circuit with VA = 0V, VB = 0V, and VC = 3V. What are the
simulated value of Vout1 and Vout2 ? Does this circuit function correctly? Why
or why not? How can we make the circuit function correctly?You may represent
a logic 0 with a voltage less than 0.8 V and a logic 1 with a voltage greater than
2.2 V.
4. Redesign the circuit by using an appropriate value of RAN D . Show that the
circuit is functional by simulating the circuit with the chosen value of RAN D .
5. Finally, build the circuit on a breadboard and measure Vout1 and Vout2 under
different combinations of VA , VB and VC .
VA (V )
VB (V )
VC (V )
0
0
0
0
0
3.0
0
3.0
0
0
3.0
3.0
3.0
0
0
3.0
0
3.0
3.0
3.0
0
3.0
3.0
3.0
Vout1,sim
Vout2,sim
Vout1,meas
Table 4.3: Truth table for 3-input OR2-AND2.
Vout2,meas
SUBMISSION CHECKLIST
4.8
25
Submission Checklist
The following items are due in the beginning of the next lab.
1. Submit Table 4.1. (1 points)
2. Submit Table 4.2. (1 points)
3. What are the appropriate value of ROR and RAN D for the 3-input OR2-AND2
circuit? How are these values determined? What is the thought process behind
choosing these values?(4 points)
4. Submit Table 4.3. (3 points)
5. Survey questions (2 points)
(a) Were the objectives of this lab clear?
(b) Was the instruction clear? Are there any typos or grammatical mistakes you
wish to point out?
(c) Did you encounter any problem using Cadence?
(d) Did you encounter any problem building the logic gates?
CHAPTER 5
BIPOLAR JUNCTION TRANSISTORS
5.1
Objectives
After completing this lab, you will be able to
1. Using the diode check feature on the multimeter to deduce the terminals of a
BJT.
2. Measure β of a BJT.
5.2
Parts
One 2N3904 npn transistor (Mouser 512-2N3904TA)
One 100 Ω resistor
One 33 kΩ resistor
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5.3
BIPOLAR JUNCTION TRANSISTORS
Testing a Transistor with a DMM
A digital multimeter can be used as a fast and simple way to check a transistor for
open or shorted junction. In Figure 5.1(a), the positive lead of the meter is connected
to the base of an npn transistor and the negative lead is connected to the emitter to
forward-bias the base-emitter junction of an NPN transistor. A reading of 0.7 V is
shown on the multimeter. In Figure 5.1(b), the positive lead of the meter is connected
to the emitter while the negative lead is connected to the base, a reading of ”OL” is
shown on the multimeter.
Figure 5.1: Test of the base-emitter junction
5.4
Determine Terminals of a BJT
1. We will deduce the terminals of a 2N3904 transistor using a multimeter’s ”diode
check” function in this exercise.
2. We need to collect some data before we can deduce a transistor’s terminals
systematically. Refer to the transistor shown in Figure 5.2. Use a meter to
measure and record the measurement results in Table 5.1.
Figure 5.2: A Generic BJT
THE BJT CHARACTERISTIC CURVE
Red Probe
Black Probe
1
2
2
1
1
3
3
1
2
3
3
2
29
Voltage
Table 5.1: Measurements
3. Let’s focus on readings that produce forward bias voltages. Which wire is common in all “forward bias” readings? If a transistor is a PNP transistor, the probe
that is common in all “forward bias” readings is black; if a transistor is an NPN
transistor, the probe that is common in all ”forward bias” readings is red. Is
2N3904 a PNP transistor or an NPN transistor?
4. Since the emitter is more highly doped than the collector, a base-emitter junction reading will produce a higher forward voltage drop. According to the measurement results in Table 5.1, which wire is the emitter and which wire is the
collector?
5. Google for a spec sheet of a 2N3904 transistor, and verify that you have identified the terminals of a 2N3904 transistor correctly.
5.5
The BJT Characteristic Curve
1. Measure the resistance of the resistors in Figure 5.3 and record the results in
Table 5.2.
Resistor
Listed Value
Measured Value
R1
R2
Table 5.2: Measured resistor values
2. Connect the common-emitter configuration illustrated in Figure 5.3. Start with
both power supplies set to 0 V. The purpose of R1 is to limit base current to
a safe level and to allow indirect determination of the base current. Slowly
increase VBB until VR1 , the voltage across R1 , is 3.3 V.
Question: According to Ohm’s law, what is the current through R1 ?
30
BIPOLAR JUNCTION TRANSISTORS
100Ω
R2
C
R1
+ V
− CC
B
33kΩ
VBB +
−
E
Figure 5.3: A Common Emitter Amplifier
3. Without disturbing the setting of VBB , slowly increase VCC until 2.0 is measured between the transistor’s collector and emitter. This voltage is VCE . Measure and record VR2 for this setting. Record VR2 in Table 5.3.
4. Compute the collector current, IC , by applying Ohm’s law to R2 . Use the measured voltage, VR2 , and the measured resistance, R2 , to determine the current.
Note that the current in R2 is the same as IC for the transistor. Enter the computed collector current in Table 5.3.
VCE
IB from step 2-5
meas.
VR2 (Meas.)
IC (Calc.)
IB from step 6-7
VR2 (Meas.)
IC (Calc.)
IB from step 8-9
VR2 (Meas.)
IC (Calc.)
2.0 V
4.0 V
6.0 V
8.0 V
Table 5.3: IB and IC of a BJT.
5. Without disturbing the setting of VBB , increase VCC until 4.0 V is measured
across transistor’s collector to emitter. Measured and record VR2 for this setting.
Compute the collector current by applying Ohm’s law as in the previous step.
Continue in this manner for each of the values of VCE listed in Table 5.3.
6. Reset VCC for 0 V and adjust VBB until VR1 is 4.95 V.
According to Ohm’s law, what is the current through R1 ?
7. Without disturbing the setting of VBB , increase VCC until 2.0 V is measured
across transistor’s collector to emitter. Measure and record VR2 for this setting.
Compute the collector current by applying Ohm’s law as in the previous step.
Continue in this manner for each of the values of VCE listed in Table 5.3.
SUBMISSION CHECKLIST
31
8. Reset VCC for 0 V and adjust VBB until VR1 is 6.6 V.
According to Ohm’s law, what is the current through R1 ?
9. Without disturbing the setting of VBB , increase VCC until 2.0 V is measured
across transistor’s collector to emitter. Measure and record VR2 for this setting.
Compute the collector current by applying Ohm’s law as in the previous step.
Continue in this manner for each of the values of VCE listed in Table 5.3.
10. Use Excel to plot three collector characteristic curve using the data tabulated
in Table 5.3. The collector characteristics curve is a graph of VCE versus IC
for a constant base current. Choose a scale of IC that allows the largest current
observed to fit on the graph. Label each curve with the base current it represents.
11. Use the data you collected in Table 5.3 to determine the β for the transistor
biased at various VCE and IB . Record the calculated β values in Table 5.4.
Current Gain, β
VCE
IB from step 2-5
IB from step 6-7
2.0 V
4.0 V
6.0 V
8.0 V
Table 5.4: Current Gains
5.6
Submission Checklist
1. Submit Table 5.1. (1 point)
2. Submit Table 5.3. (2 points)
3. Submit Table 5.4. (3 points)
4. Submit IC verus VCE plot. ( 2 points)
IB from step 8-9
CHAPTER 6
NAND GATE
6.1
References
1. Section 4.5, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
2. Transistor-transistor logic [Online].
Available: http://en.wikipedia.org/wiki/Transistor-transistor_logic
6.2
Objectives
After completing this lab, you will be able to
1. Analyze a transistor-transistor logic (TTL) circuit.
2. Simulate a TTL circuit in Cadence.
3. Build a TTL circuit on a breadboard.
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6.3
NAND GATE
Analysis
1. The schematic of a NAND gate implemented with three resistors, three npn
transistors, and one diode is shown in Figure 6.1. We assume in this experiment
that the turn-on voltage for a pn junction is 0.65 V, i.e. VD,on = 0.65 V and
VBE,on = VBC,on = 0.65 V.
R1
RC
Y
QA
+ V
− A
QB
+ V
− B
+ V
− CC
Q1
D1
RB
Figure 6.1: A NAND gate implemented with a BJT.
2. In order to get a “1” at the output of this circuit, VY = VCC . In other words, Q1
must be in the cut-off mode, i.e. VBE,1 = 0.0 V and VBC,1 = 5 V. The output
of an NAND gate is a “1” as long as one of the inputs is a “0”. Let’s analyze
the circuit in Figure 6.1 assuming that VA = 0 V and VB = 5 V.
(a) If VA = 0 V, is the base-emitter junction of QA forward biased?
(b) What should be the DC voltage at the base of QA ?
(c) What should be the DC voltage at the base of QB ?
(d) Recall that VB = 5 V, is the base-emitter junction of QB forward biased or
reverse biased?
(e) Assuming that Q1 is off, will there be a base current flowing into the base
of Q1 ?
(f) Assuming that Q1 is off, i.e. VBE,1 = 0 V, will there be a current flowing
through RB ?
(g) Is there a current flowing through D1 ?
(h) Assuming that the diode (D1 ) is ideal, what should be the voltage at the
collector of QA ?
DESIGN AND SIMULATION
35
(i) Is the base-collector junction of QA forward biased or reverse biased?
(j) What is the operating mode of QA ? (active, saturation or cut-off)
(k) Is the base-collector junction of QB forward basied or reverse biased?
(l) Which mode of operation is QB in? (active mode, saturation mode, reverseactive mode, cut-off mode.)
3. In order to get a “0” at the output of the circuit in Figure 6.1, VY = 0 V. Q1
must be on, i.e. VBE,1 = 0.65 V. Both inputs should be high. We assume that
VA = VB = VCC .
(a) What is the status of the base-emitter junction of QA ? i.e. is it forward
biased or reverse biased?
(b) What is the direction of the base current of Q1 ? into the base or out of the
base?
(c) Will D1 be conducting?
(d) Is there a current leaving the collector terminal of QA ?
(e) Is the base-collector junction of QA forward biased or reverse biased?
(f) What is the mnode of operation of QA ? (active, saturation, cut-off)
(g) Is there a current leaving the collector terminal of QB ?
(h) Is the base-collector junction of QB foward biased or reverse biased?
(i) What is the mode of operation for QB ? (active, saturation, reverse saturation, or cut-off)
(j) If VBE,1 = 0.65 V, what should be the voltage at the collector of QA ?
(k) If VBE,1 = 0.65 V, what should be the voltage at the base of QA ?
6.4
Design and Simulation
1. Build the 2-input NAND gate in Figure 6.1 in Cadence. You may assume the
following values when constructing the circuit:
(a) VCC is equal to 5 V.
(b) 2n3904 NPN transistors are used and one 1n4001 diode is used. You can
use the npn transistor from the analogLib library. Please download the
model for the 2n3904 transistor from the ES231 course website and include the model file in the ADE.
(c) R1 is equal to 2 KΩ and RB is equal to 1.1 KΩ.
(d) RC is equal to 10 KΩ.
2. Build the circuit in Cadnece. Verify the functionality of the NAND gate by
showing VA , VB , and VY in a truth table.
36
NAND GATE
3. Does the circuit behave as a NAND gate? Are you able to get VY to rise to a
sufficient level? VY > 4.0 V is required for a “1” and VY < 1.0 V is required
for a “0”. (Hint: the output resistance of a BJT is not ∞. How would you adjust
RC so as to adjust VY appropriately?
4. Resimulate the circuit and record the VA , VB and VY of the NAND gate.
6.5
Hardware Implementation
1. Implement the NAND gate on a breadboard.
2. Measure VA , VB and VY . Compare your results with Cadence simulation.
6.6
Submission Checklist
1. Submit the schematic of the NAND gate. (2 points)
2. Submit the followings for simulation and breadboard measurement.
(a) A truth table showing both simulation results and measurement results.
Please show VA , VB , and VY in the table. (2 points)
(b) Summarize the mode of operation for QA , QB and Q1 when VA = VB = 5
V. (2 points)
(c) Summarize the mode of operation for QA , QB and Q1 when VA = 0V and
VB = 5 V. (2 points)
VA
VB
0.0 V
0.0V
0.0 V
5.0V
5.0 V
5.0V
5.0 V
0.0V
VY,meas
VY,sim
Table 6.1: Truth Table for the NAND gate
CHAPTER 7
DC OPERATING POINT OF AN FM
WIRELESS MICROPHONE CIRCUIT
7.1
References
1. Section 5.1-5.2, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
2. FM Wireless Microphone Kit, Model K-30/AK-710, 1994.
3. Slides from 03.04.14.
7.2
Objectives
After completing this lab, you will be able to
1. Calculate DC operating point using iteration.
2. Calculate small signal parameters.
3. Obtain DC operating point using Cadence.
4. Obtain small signal parameters using Cadence.
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DC OPERATING POINT OF AN FM WIRELESS MICROPHONE CIRCUIT
7.3
Analysis
The schematic of AK-710 FM wireless microphone circuit is shown in Figure 6.1.
The circuit is consisted of five building blocks: the microphone circuit, audio amplifier, radio frequency oscillator, radio frequency amplifier, and the antenna. The audio
amplifier is constructed with R2 , R6 , R7 , R3 and Q1 . The audio signal is injected
into the base of Q1 . The amplified audio signal at the collector of Q1 modulates
the base-collector capacitance of Q2 and produces the FM modulated signal at the
collector of Q2 . The radio frequency (RF) oscillator is constructed from R4 , C3 , R8 ,
L1 and Q2 . L1 is a 100 nH inductance constructed from a 22 AWG copper wire. The
FM modulated signal from Q2 is amplified by the RF amplifier, which is consisted
of R9 , R5 and Q5 . C1 and C2 are coupling capacitors for the audio signal. C5 and
C6 provides the positive feedback which is necessary to jump start the oscillation.
C4 couples the FM modulated signal to the RF amplifier. C3 ensures that only audio
signal is present at the base of Q2 .
Figure 7.1: Schematic of AK-710 FM wireless microphone kit.
7.3.1
Constants and Equations
1. IC = IS exp(VBE /VT )
(a) IS = 6.73 × 10−15 A. This value is obtained from 2n3904.m.
(b) VT = 25 mV
2. gm = IC /VT
ANALYSIS
39
3. rπ = β/gm , assume β = 150.
4. ro = VA /IC , VA = 74.03V . VA is obtained from 2n3904.m
7.3.2
DC operating point analysis of the audio amplifier
It can be shown that by subtracting VE1 from VB1 , VBE1 , the base-emitter voltage
of Q1 is
R6
β+1
VBE1 = VCC
−
IC1 R7
(7.1)
R6 + R2
β
Next, using the expression for IC1 , we can obtain a second expression for VBE1 .
Setting both expressions of VBE1 equal to each other, we can iterate to solve IC1 .
VT ln
IC1
R6
β+1
= VCC
−
IC1 R7
IS
R6 + R2
β
(7.2)
Start by solving for IC1 . Next, use IC to calculate VC1 , VE1 , VB1 , gm1 , rπ1 , and ro1 .
VC1 and VE1 can be obtained using the following equations:
VC1 = VCC − IC1 R3
(7.3)
β+1
IC1 R7
β
(7.4)
VE1 =
VB1 = VE1 + VT ln
Calculation
IC1
IS
Cadence
IC1
VC1
VE1
VB1
gm1
rπ1
ro1
β
Table 7.1: DC Operating Point Calculation for Q1 .
(7.5)
40
7.3.3
DC OPERATING POINT OF AN FM WIRELESS MICROPHONE CIRCUIT
DC operating point analysis of the RF oscillator
It can be shown that by subtracting VE2 from VB2 , VBE2 , the base-emitter voltage is
VBE2 = VCC −
β+1
IC2
IC2 R8 −
R4
β
β
(7.6)
Using the expression for IC2 we can obtain a second expression for VBE2 . Setting
both expression of VBE2 equal to each other, we can iterate to solve IC2 .
VT ln
β+1
IC2
IC2
= VCC −
IC2 R8 −
R4
IS
β
β
(7.7)
Next, use IC2 to calculate VC2 , VE2 , VB2 , gm2 , rπ2 , and ro2 . VE2 and VB2 can be
obtained using the following equations:
VB2 = VCC −
VE2 =
IC2
R4
β
β+1
IC2 R8
β
Calculation
(7.8)
(7.9)
Cadence
IC2
VE2
VB2
gm2
rπ2
ro2
β
Table 7.2: DC Operating Point Calculation for Q2 .
7.3.4
DC operating point analysis of the RF amplifier
It can be shown that by subtracting VE3 from VB3 , VBE3 , the base-emitter voltage is
VBE3 = VCC −
IC3
R9
β
(7.10)
Using the expression for IC3 we can obtain a second expression for VBE3 . Setting
both expression of VBE3 equal to each other, we can iterate to solve IC3 .
VT ln
IC3
IC3
= VCC −
R9
IS
β
(7.11)
SIMULATION
41
Start by solving for IC3 . Next, use IC3 to calculate VC3 , VE3 , VB3 , gm3 , rπ3 , and
ro3 . VC3 and VE3 can be obtained using the following equations:
VC3 = VCC − IC3 R5
VB3 = VT ln
Calculation
IC3
IS
(7.12)
(7.13)
Cadence
IC3
VC3
VB3
gm3
rπ3
ro3
β
Table 7.3: DC Operating Point Calculation for Q3 .
7.4
Simulation
1. Build AK-710 FM wireless microphone circuit in Cadence. You may assume
the following values when constructing the circuit:
(a) VCC is equal to 3 V.
(b) 2n3904 NPN transistors are used. You can use the npn transistor from the
analogLib library.
2. Run the DC operating point analysis. Annotate the schematic to get the DC
operating point displayed on the schematic.
3. Finally, display the small signal parameters next to the transistors and record
the values in Table 7.1, Table 7.2, and Table 7.3.
7.5
Submission Checklist
1. Derive Eq. 7.2, Eq. 7.7 and Eq. 7.11. (3 points)
2. Submit Table 7.1, Table 7.2, and Table 7.3. (5 points)
CHAPTER 8
SMALL SIGNAL ANALYSIS OF AN FM
WIRELESS MICROPHONE CIRCUIT
8.1
References
1. Chapter 5, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
2. FM Wireless Microphone Kit, Model K-30/AK-710, 1994.
3. Lecture slides from 03.04.14 and 03.12.14.
8.2
Objectives
After completing this lab, you will be able to
1. Calculate the voltage gain of a common-emitter amplifier.
2. Perform transient simulation in Cadence.
3. Determine the voltage gain from transient simulation.
4. Determine the voltage gain from breadboard measurement.
Electronics I Laboratory Manual, First Edition.
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8.3
SMALL SIGNAL ANALYSIS OF AN FM WIRELESS MICROPHONE CIRCUIT
Data from last week
We are going to calculate the gain of the audio amplifier shown in Figure 8.1. We
have already calculate the small signal parameters from last week. Before you start
the lab, please record the small signal paramters from last week in Table 8.1. We
have also included VC1 , VE1 , and VB1 in Table 8.1 so you can use these values to
debug your circuit circuit.
4.7 kΩ
R3
Vout
27 kΩ
0.1 uF
R1
Vin
+
3V − VCC
2N 3904
C1
10 kΩ
Vs
R6
1500 Ω
R7
Figure 8.1: The audio amplifier stage of AK-710 FM microphone.
Calculation
Cadence
IC1
VC1
VE1
VB1
gm1
rπ1
ro1
β
Table 8.1: DC Operating Point Calculation for Q1 .
8.4
Analysis
The gain of the amplifier is defined as Vout /Vs , where Vout is the small signal voltage
at the output and Vin is the small signal voltage at the input. We are going to calculate
the gain of the audio amplifier in two steps using the following equation:
Vout Vin
Vout
=
VS
Vin VS
(8.1)
SIMULATION
45
1. Calculation of Vin /VS :
(a) The range of audio frequency. We are going to assume that the highest
frequency that we can handle with this audio amplifier is 20 kHz and the
lowest frqeuency we can handle is 200 Hz. What is the impedance of C1 at
20 kHz? What are the impedances of C1 at 2 kHz and 200 Hz? (2 points)
(b) What is the small signal resistance looking into the base of Q1 (Rb,in )? (1
point)
(c) What is the relationship between Rb,in , R1 and R2 ? (1 point)
(d) What the transfer function from VS to Vin ? i.e. What is Vin /VS ? (1 point)
(e) Is this audio amplifier a good bass amplifier? (1 point)
2. What is Vout /Vin ? (hint: use the gain expression for the common-emitter amplifier) (1 point)
3. What is Vout /VS ?
8.5
Simulation
1. Build the common-emitter amplifier shown in Figure 8.1 in Cadence. Please use
vsin from the analogLib library as the sinusoidal voltage source. Please
use 50mV for Amplitude and use 20 kHz for frequency.
2. Go to Analylses in the Analog Design Environment window and select
trans in order to run the transient analysis.
3. Plot Vout , Vin , and VS . You can plot these waveforms by selecting Results→Direct Plots→Transient Signals.
Please generate these plots at 200 Hz, 2 kHz and 20 kHz. (2 points)
4. Calulate Vout /Vin and Vin /VS at 200 Hz, 2 kHz and 20 kHz. (2 point)
8.6
Measurement
1. Build the circuit on a breadboard.
2. Measure Vout , Vin , and VS with the source set to 200 Hz, 2 kHz, and 20 kHz.
Please set the amplitude of the sinewave to 50 mV (or 100 mVpp). (The output
load of wavegen should be set to high Z by default. You can verify this by
pressing wavegen and Settings.)
8.7
Submission Checklist
1. Please answer all of the questions in the lab.
2. In addition, compare the analysis, simulation and measurement values of Vout /Vin ,
Vin /VS , and Vout /VS at 200 Hz, 2 kHz, and 20 kHz.
CHAPTER 9
ONE-TRANSISTOR FM TRANSMITTER
9.1
References
1. Chapter 5, B. Razavi, Fundamentals of Microelectronics, Wiley, 2008.
2. FM Wireless Microphone Kit, Model K-30/AK-710, 1994.
9.2
Objectives
After completing this lab, you will be able to
1. Build a simple one-transistor FM transmitter.
2. Design and build a coil inductor.
3. Use a spectrum analyzer.
Electronics I Laboratory Manual, First Edition.
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48
9.3
ONE-TRANSISTOR FM TRANSMITTER
Preliminary Calculation
We will build a one-transistor FM transmitter shown in Figure 9.1 in this experiment.
R8 and R4 set the DC bias current for the oscillator. In order to jump start the oscillation, we provide positive feedback from Vosc to the emitter terminal by connecting
C5 in series with C6 . C3 removes any unwanted oscillation signal coupled from
Vosc to the base of the BJT. C1 an audio signal to be injected to the base terminal so
that the frequency of the oscillator can be modulated. The frequency of the oscillation is determined by the value of the inductor as well as the equivalent capacitance
connected in parallel with the inductor. The equivalent capacitance includes fixed
capacitance (such as C5 and C6 ) and variable capacitance, such as the base-collector
capacitance.
100 nH L
47 kΩ
R4
C5
2N 3904
100uF
12pF 3V + VCC
−
C1
Vs
1 nF
C3
1000 Ω
R8
C6
33pF
Figure 9.1: One-Transistor FM transmitter.
9.3.1
Coil Inductor
It is difficult to get a variable inductor. So We will build a 100 nH coil inductor constructed from a 22 gauge wire. To determine the geometry of the 100 nH coil inductor, we use the inductance calculator from http://www.66pacific.com/calculators/coil_calc.aspx.
1. What should be the number of turns, diameter, and length of the 100 nH coil
inductor?
9.3.2
Base-Collector Capacitance
This exercise is optional. The base-collector capacitance is determined by the the
width of the base-collector depletion region. The width of the base-collector region
is changed by the bias across the base-collector junction. We change the frequency
MEASUREMENT
49
of the oscillator by introducing a voltage change at the base of the the transistor.
You can observe the extent to which the base-collector capacitance changes with the
base-collector voltage by sweeping Vin in Figure 9.2 from 0 V to 3 V at 0.2 V step
and recording Cµ (cmu in the small signal parameter) VBC at each voltage step in
Cadence.
1 kΩ
RC
+
3V −
2N 3904
+ V
− in
Figure 9.2: Circuit setup for measuring CBC in Cadence.
9.4
Measurement
1. Build the one-transistor FM transmitter shown in Figure 9.1.
2. Determine the approximate oscillation frequency by displaying the collector
voltage on the spectrum analyzer. (You should short the VS to ground in this
experiment.) If the oscillation frequency does not fall into the FM band, you
may have to adjust the geometry of the inductor until the circuit oscillate at an
FM frequency.
3. Next, use the function generator to generate a tone of 880 Hz and feed it to the
oscillator through C1 . Tune the FM radio (receiver) to the frequency that you
have observed on the spectrum analyzer. Are you able to hear the tone at 880
Hz?
CHAPTER 10
APPLICATION OF MOS TRANSISTORS
IN DIGITAL CIRCUITS
10.1
References
1. Chapter 15 and Chapter 6, B. Razavi, Fundamentals of Microelectronics, Wiley,
2008.
10.2
Objectives
After completing this lab, you will be able to
1. Build a resistively loaded NMOS/PMOS inverter.
2. Build a CMOS inverter.
3. Analyze digital circuits implemented in CMOS.
4. Simulate CMOS circuits in Cadence.
5. Build the CMOS circuits using ALD1106 and ALD1107.
Electronics I Laboratory Manual, First Edition.
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APPLICATION OF MOS TRANSISTORS IN DIGITAL CIRCUITS
10.3
Resistively loaded NMOS Inverter
10.3.1
Analysis and Simulation
NMOS transistors are frequently used as switches in digital circuits. In this experiment, we explore its use in the context of an inverter shown in Figure 10.1.
Please download the ald1106.m model from the course website and save it in the
/home/r2d2/models/discrete/ directory.
VCC
VCC
RD
10kΩ
Vout
ALD1106
Vin +
−
(a) Schematic model.
RD
10kΩ
Vout
ALD1106
(b) Switch model.
Figure 10.1: Resistively loaded NMOS.
1. Enter the schematic in Cadence Virtuoso. Take a look at the tutorials posted
at the course website if you need step-by-step instruction. VCC = 5 V in this
exercise. Please remember to connect the “body” terminal to ground.
2. Sweep Vin from 0 V to 5 V in 0.2 V increment. Plot Vout as a function of Vin .
3. When Vin is either a logic “1” or a logic “0”, the transistor can be modeled as
either a closed switch or an open switch.
(a) What is Vout when the switch is closed?
(b) What is Vout when the switch is opened?
(c) According to the simulation, is the closing of the switch activated by a logic
“1” or a logic “0”?
10.3.2
Measurement
1. Construct the circuit on a breadboard. Study the datasheet carefuly to determine
the appropriate DC voltage for V − and V + .
2. Connect Vin to one of the outputs terminals of the random number generator
circuit. Observe the output voltage on the mixed-signal scope. Does the output
behave as predicted?
RESISTIVELY LOADED PMOS
10.4
10.4.1
53
Resistively loaded PMOS
Analysis and Simulation
PMOS transistors are frequently used as switches in digital circuits. In this experiment, we explore its use in the context of an inverter shown in Figure 10.2. Please
download the ald1107.m from the course website and save it in the /home/r2d2/models/discrete/
directory.
VCC
VCC
ALD1107
ALD1107
Vout
Vin +
−
RS
10kΩ
(a) Schematic model.
Vout
RS
10kΩ
(b) Switch model.
Figure 10.2: Resistively loaded PMOS.
1. Enter the schematic in Cadence Virtuoso. Take a look at the tutorials posted
at the course website if you need step-by-step instruction. VCC = 5 V in this
exercise. Please remember to connect the “body” terminal to VCC .
2. Sweep Vin from 0 V to 5 V in 0.2 V increment. Plot Vout as a function of Vin .
3. When Vin is either a logic “1” or a logic “0”, the transistor can be modeled as
either a closed switch or an open switch as shown in Figure 10.2b.
(a) What is Vout when the switch is closed?
(b) What is Vout when the switch is opened?
(c) According to the simulation, is the closing of the switch activated by a logic
“1” or a logic “0”?
10.4.2
Measurement
1. Construct the circuit on a breadboard. Study the datasheet carefuly to determine
the appropriate bias voltage for V − and V + .
2. Connect Vin to one of the outputs terminals of the random number generator
circuit. Observe the output voltage on the mixed-signal scope. Does the output
behave as predicted?
54
APPLICATION OF MOS TRANSISTORS IN DIGITAL CIRCUITS
10.5
CMOS Inverter
10.5.1
Analysis
We examine the operation of a CMOS inverter in Figure 10.3. We start by asking the
following questions:
1. If Vin is equal to VCC (i.e. a logic “1”), what is the equivalent switch model for
M2 ? Is it closed or open? What is the equivalent switch model for M1 ? What
is Vout in this instance?
2. If Vin is equal to 0 V (i.e. a logic “0”), what is the equivalent switch model for
M1 and M2 ? Is it closed or open? What is Vout in this instance?
VCC
M2
Vout
M1
Vin +
−
Figure 10.3: CMOS Inverter.
10.5.2
Simulation
Enter the schematic for the CMOS inverter in Cadence. Demonstrate that the circuit
does indeed behave as a CMOS inverter by feeding a logic “1” and a logic “0” to Vin .
Please remember to connect the “body” terminal of the NMOS transistor to ground
and the “body” terminal of the PMOS transistor to VCC .
10.5.3
Measurement
1. Construct the circuit on a breadboard. Study the datasheet carefuly to determine
the appropriate bias voltage for V − and V + .
2. Connect Vin to one of the outputs terminals of the random number generator
circuit. Observe the output voltage on the mixed-signal scope. Does the output
behave as predicted?
A TWO-INPUT CMOS LOGIC GATE
10.6
55
A Two-Input CMOS Logic Gate
The schematic of a mysterious two-input CMOS logic gate is shown in Figure 10.4.
Please take the following approach to verify the functionality of the circuit systematically.
1. First, deduce the logic implemented by this circuit by replacing each transistor
by its equivalent switch model. You can start by constructing a truth table for
this circuit and record the ideal Vout for each input combination in Table 10.1.
(1 point)
2. Simulate the behavior of the circuit using Cadence. Please record the result in
Table 10.2 (1 point)
3. Build the circuit using ALD1106 and ALD1107 transistors. Please record the
measurement results in Table 10.3. (1 point)
4. Are you able to conclusively determine the function of this circuit? What does
it do? (1 point)
5. Finally, use the outputs of the random number gnerator to test the circuit. Attach
a screen capture to demonstrate the functionality of the circuit. (1 point)
VCC
M4
M2
Vout
VA +
− V +
B −
M1
M3
Figure 10.4: Schematic of a mysterious 2-input CMOS logic gate.
56
APPLICATION OF MOS TRANSISTORS IN DIGITAL CIRCUITS
VA
VB
0
0
0
VCC
VCC
0
VCC
VCC
M1
M3
M2
M4
Vout
Table 10.1: Analysis of the two-input CMOS circuit.
VA
VB
0
0
0
VCC
VCC
0
VCC
VCC
M1
M3
M2
M4
Vout
Table 10.2: Simulation results of the two-input CMOS circuit.
VA
VB
0
0
0
VCC
VCC
0
VCC
VCC
M1
M3
M2
M4
Vout
Table 10.3: Measurement results of the two-input CMOS circuit.

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