www.arm.com ARM® CoreLink™ Cache Coherent Network (CCN) Family Scalable efficient interconnect for compelling solutions Growth in mobile computing and the Internet of Things is connecting more devices and aggregating more data across the network, and that demands an increasingly flexible and efficient computing infrastructure. The CoreLink CCN family offer the solution with scalable, high performance cache coherency for ARM Cortex® processors, memory and IO such as accelerators and network interfaces. The CoreLink CCN interconnects are designed for the latest AMBA® 5 CHI protocol providing high frequency, non-blocking data transfers and integrated Level 3 Cache and Snoop Filter Cache coherency across processors, IO and accelerators The CoreLink CCN-512, CCN-508, CCN-504, CCN-502 and CCI-400 interconnects provide a spectrum of implementations scaling from costefficient, minimal area, single core systems, up to the highest performance Mid-range Cost-efficient High-end CCN-512 System Performance CCN-508 CCN-504 CCN-502 AMBA 5 CHI AMBA 4 ACE CCI-400 0MB Level-3 Cache Size 32MB 20 GB/s DDR Bandwidth 75 GB/s 0.2 Tb/s On-chip Bandwidth 1.8 Tb/s 48 core systems. All of the CCN family offer a common architecture with integrated configurable L3 cache which can operate as a system cache allowing allocation of IO traffic. The CoreLink CCN family and companion CoreLink DMC-520 Dynamic Memory Controller are designed for high reliability with integrated RAS and ECC features to protect data. Advanced end to end Quality-of-Service (QoS) mechanisms enable the control required for maximum bandwidth and minimum latency. CoreLink CCN-502 is the most costand power-efficient solution in the CCN family offering 70% area reduction over CoreLink CCN-504 at 1MB. Applications may include small cell base stations and sub-10W Power-over-Ethernet wireless access points. CoreLink CCN-512 offers the highest compute density, scaling up to 12 cluster, 48 core, 64-bit ARMv8-A, systems. Applications may include macro cell base stations, data center and servers. System Size Feature CCN-502 CCN-504 CCN-508 CCN-512 Key Benefits Smallest CCN interconnect, Optional L3 Highest performance 4 cluster interconnect 8 cluster interconnect, high IO bandwidth 12 cluster interconnect, highest compute performance L3 cache support 0 to 8 MB 1 to 16 MB 1 to 32 MB 1 to 32 MB Processor Clusters 1-4 Cortex -A53 / Cortex-A57 1-4 Cortex-A53 / Cortex-A57 1-8 Cortex-A53 / Cortex-A57 1-12 Cortex-A53 / Cortex-A57 IO (AXI4/ ACE-Lite) Up to 9 Up to 18 Up to 24 Up to 24 DDR3/DDR4 1 to 4 channels with DMC-520 1 to 2 channels with DMC-520 1 to 4 channels with DMC-520 1 to 4 channels with DMC-520 ® The Architecture for the Digital World® Extending the ARM CoreLink Cache Coherent Network Family Key Features of the CCN Family: •Integrated Level 3 Cache and Snoop Filter •Designed for the 64-bit ARMv8-A •Scalable architecture offering software The CoreLink CCN-502 and CCN-512 are the newest members of the Cache Coherent Network family. processors including Cortex-A57 and Cortex-A53 compatibility •Native AMBA 5 CHI interfaces •Part of complete solution including providing high frequency, nonblocking data transfers Cortex processors, CoreLink DMC-520 Dynamic Memory Controller, CoreLink MMU-500 System MMU and CoreLink GIC-500 Interrupt Controller. •End-to-end QoS and RAS CoreLink CCN-502 High Performance, Small Footprint 10-40 GbE PCIe GIC-500 DSP DSP DSP SATA USB NIC-400 Cortex-A57 Cortex-A57 Cortex-A53 I/O Virtualisation CoreLink MMU-500 Cortex-A53 CoreLink™ CCN- 502 Cache Coherent Network 0-8MB L3 cache Snoop Filter Memory Controller DMC-520 Memory Controller DMC-520 Memory Controller DMC-520 Memory Controller DMC-520 x72 DDR4-3200 x72 DDR4-3200 x72 DDR4-3200 x72 DDR4-3200 Network Interconnect NIC-400 Flash SRAM GPIO PCIe CoreLink CCN-512 Maximize Compute Density GIC-500 Cortex-A57 Cortex-A57 Cortex-A57 Cortex-A57 Cortex CPU or CHI master Cortex-A53 Cortex-A53 10-40 GbE PCIe DPI ACE Cortex-A53 Cortex CPU or CHI master Cortex-A53 Cortex CPU or CHI master Cortex CPU or CHI master DSP DSP DSP PCIe DPI Crypto AHB SATA USB NIC-400 I/O Virtualisation CoreLink MMU-500 CoreLink™ CCN- 512 Cache Coherent Network Snoop Filter 1-32MB L3 cache Memory Controller DMC-520 Memory Controller DMC-520 Memory Controller DMC-520 Memory Controller DMC-520 Network Interconnect NIC-400 x72 DDR4-3200 x72 DDR4-3200 x72 DDR4-3200 x72 DDR4-3200 Flash SRAM Network Interconnect NIC-400 GPIO PCIe www.arm.com/products/system-ip/interconnect ARM, ARMPowered, Artisan, StrongARM, Thumb,Multi-ICE,ModelGen, PrimeCell, SecurCore, PrimeXsys, RealView, TrustZone, Jazelle, ARM7TDMI, ARM9TDMI, ARMulator AMBA, Connected Community and The Architecture for the DigitalWorld are registered trademarks of ARMLimited. Cortex, AXI, AHB, ARM7, ARM7TDMI-S, ARM7EJ-S, ARM720T, ARM740T, ARM9, ARM9TDMI, ARM920T, ARM922T, ARM940T, ARM9E, ARM9E-S, ARM926EJ-S, ARM946ES, ARM966E-S, ARM968E-S, ARM996HS, ARM10, ARM1020E, ARM1022E, ARM1026EJS, ARM11, ARM1136J-S, ARM1136JF-S, ARM1156T2-S, ARM1156T2F-S, ARM1176JZ-S, DesignStart, ARM1176JZF-S, EmbeddedICE, EmbeddedICE-RT, AMBA, ARM Development Suite, ETM, ETM7, ETM9, ETM10, ETM10RV, ETM11, Embedded Trace Macrocell, Embedded Trace Buffer, ETB, ETB11, Embedded Trace Kit, Integrator, JTEK,Mali,MultiTrace,MPCore,MOVE,OptimoDE,AudioDE, SecurCore, SC100, SC110, SC200, SC210, SC300, SC000 are trademarks of ARMLimited. Java is a trademark of SunMicrosystems, Inc. XScale is a trademark of Intel Corporation. All other brand names or product names are the property of their respective holders. All other trademarks and trade names are the property of their respective holders. “ARM” is used to represent ARM Holdings plc (LSE: ARM and NASDAQ: ARMHY); its operating company ARM Limited; and the regional subsidiaries: ARM, Inc.; ARMKK; ARMKorea Ltd.; ARMTaiwan Limited; ARMFrance SAS; ARMConsulting (Shanghai) Co. Ltd.; ARMBelgiumN.V.; AXYS Design Automation Inc.; ARMGermany GmbH; ARMEmbedded Technologies Pvt. Ltd.; ARMNorway, AS; and ARM Sweden AB. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information. www.arm.com
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