More on Verilog Behavior Coding

Part I: Verilog Coding Concepts
More on Behavior
Model for Verilog HDL
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Chih-Tsun Huang (黃稚存)
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Department of Computer Science
National Tsing Hua University
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Module Partition
Adding Structure
Horizontal Partition
Vertical Partition
Parallel Operations
Multiplexor-based Operations
Vendor independent HDL
Proper don't care
*This Materials are provided by Jing-Reng Huang.
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Module Partition
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Keep Critical path within a module
All module outputs are registered
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Well-select the gate count number within a
module
Prepare to reuse hierarchical modules
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Focus:
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Module:
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Adding Structure
Focus:
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Modeling:
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Explicit specify the separate assignment
Make use of the parentheses
Build the design as your knowledge
Don't rely on CAD tools
Separated combinational and Sequential Logic
blocks
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Example: AND4
Horizontal Partition
module AND4 (in1, in2, in3, in4, out);
input in1, in2, in3, in4;
output out;
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assign out = (in1 & in2) & (in3 & in4);
// assign out = in1 & in2 & in3 & in4;
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endmodule
Module:
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Example: 16-bits Adder
Separate independent I/Os
Reduce I/O numbers
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Vertical Partition
module FA32(a0,a1,a2,sum,carry);
input a0,a1,a2;
output sum,carry;
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assign sum=a0^a1^a2;
assign carry=(a0&a1)|(a1&a2)|(a0&a2);
Focus:
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endmodule
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module ripple8(a0,a1,sum,carry_in,carry_out);
input [7:0] a0,a1;
input carry_in;
output [7:0] sum;
output carry_out;
FA32
FA32
FA32
FA32
FA32
FA32
FA32
FA32
Reduce logic complexity
Enhance reuse slice structure
Save verification time
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Module:
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FA_32_0(a0[0],a1[0],carry_in,sum[0],tc0);
FA_32_1(a0[1],a1[1],tc0,sum[1],tc1);
FA_32_2(a0[2],a1[2],tc1,sum[2],tc2);
FA_32_3(a0[3],a1[3],tc2,sum[3],tc3);
FA_32_4(a0[4],a1[4],tc3,sum[4],tc4);
FA_32_5(a0[5],a1[5],tc4,sum[5],tc5);
FA_32_6(a0[6],a1[6],tc5,sum[6],tc6);
FA_32_7(a0[7],a1[7],tc6,sum[7],carry_out);
Reuse small blocks
Save verification time
Group implementations
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Initialization small blocks
Build frequent-use blocks
Balance the design
endmodule
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Example: Divider
Parallel Operations
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X/R
Y
Adder
Q Lookup
Focus:
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Module:
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Shift
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Example: Search
Datas
CMP
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Focus:
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CMP
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Result
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CMP
Mux is preferred in CMOS design
Low power, high speed features
Module:
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CMP
Evaluate the timing requirement with area budget
before modeling
Identify parallelism
Multiplexor-based Operations
CMP
Datas
Enhance performance
Trade-off area and time
Use case
Use ? : ;
Result
CMP
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Vendor-Independent HDL
Example: Codec selection
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// Mux version
module condcodeV2 (
cc, bc, valid);
input [3:0] cc;
input [3:0] bc;
output valid;
wire n, z, v, c;
wire [7:0] ccdec;
assign {n, z, v, c} = cc;
assign ccdec = {v, n, c, c | z, n ^ v, z |
(n ^ v), z, 1’b0};
assign valid = bc[3] ^ ccdec[bc[2:0]];
endmodule
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Focus:
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Module:
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Reuse everywhere
Save design retarget time on process advance
Avoid library dependent module
Avoid process based implementations
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Example: Mux
Proper Don't Care Assignment
module mux4to1x2 (in0, in1, in2, in3, sel, out);
input [1:0] in0, in1, in2, in3;
input [1:0] sel;
output [1:0] out;
mux4to1 m4_0 (in0[0], in1[0], in2[0], in3[0], sel,
out[0]);
mux4to1 m4_1 (in0[1], in1[1], in2[1], in3[1], sel,
out[1]);
endmodule
// Module mux4to1 takes the place of vendor cell
module mux4to1 (in0, in1, in2, in3, sel, out);
input in0, in1, in2, in3;
input [1:0] sel;
output out;
wire [3:0] vec = {in3, in2, in1, in0};
assign out = vec[sel];
// instead of mux20d4 mux01 (in3, in2, in1, in0, out);
endmodule
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Focus:
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Better logic optimization
Module:
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Carefully use casez-endcase statements
Explicit don't care outputs and conditions
Better in lower level blocks
Possible simulation/synthesis mismatch
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Example: Priority Encoder
Example: Polarity
// Don't care example
module dont (a, b, o1, o2);
input [3:0] a, b;
output o1, o2;
reg o1, o2;
always @(a) begin
case (a)
0, 1, 2, 3, 4: o1 = 1'b0;
5, 6, 7, 8, 9: o1 = 1'b1;
default: o1 = 1'b0;
endcase
end
always @(b) begin
case (b)
0, 2, 4, 6, 8: o2 = 1'b0;
1, 3, 5, 7, 9: o2 = 1'b1;
default: o2 = 1'b0;
endcase
end
endmodule
module PRE_EN8_3 (A, Valid, Y);
input [2:0] A;
output Valid;
output [1:0] Y;
always @(A) begin
casez(A)
4'b 1XXX: begin Y=3; Valid =1 end
4'b 01XX: begin Y=2; Valid =1 end
4'b 001X: begin Y=1; Valid =1 end
4'b 0001: begin Y=0; Valid =1 end
default: begin Y=2'b0; Valid =0 end
endcase
end
endmodule
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Part II: Good Coding Practices
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Zero-Delay Simulation
Zero-delay Simulation
Full Sensitization List
Blocking Assignment
Clock, Reset and Set
Signal Flow
Module Interface
Multiple Assignment
FSM Modeling
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Zero delay HDL tends more reusable
Faster simulation
Prevent from timing bugs
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Full Sensitization List
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Example: Latch Inference (1/2)
module rrpriocase(request,grant,grant_next);
input [3:0] request, grant;
output [3:0] grant_next;
always @(request or grant) begin
//grant_next = grant;
// put default here to avoid latch inference
case(1) // synopsys parallel_case full_case
grant[0]:
if (request[1]) grant_next = 4’b0010;
else if (request[2]) grant_next = 4’b0100;
else if (request[3]) grant_next = 4’b1000;
else if (request[0]) grant_next = 4’b0001;
else grant_next = grant;
grant[1]:
if (request[2]) grant_next = 4’b0100;
else if (request[3]) grant_next = 4’b1000;
else if (request[0]) grant_next = 4’b0001;
else if (request[1]) grant_next = 4’b0010;
else grant_next = grant;
Rule:
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if-else if-else
case-default-endcase
Fully assign all variables in combinational with
always block
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grant[2]:
if (request[3]) grant_next = 4’b1000;
else if (request[0]) grant_next = 4’b0001;
else if (request[1]) grant_next = 4’b0010;
else if (request[2]) grant_next = 4’b0100;
else grant_next = grant;
grant[3]:
if (request[0]) grant_next = 4’b0001;
else if (request[1]) grant_next = 4’b0010;
else if (request[2]) grant_next = 4’b0100;
else if (request[3]) grant_next = 4’b1000;
else grant_next = grant;
default:
grant_next = grant;
endcase
end
endmodule
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Blocking Assignment
Example: Latch Inference (2/2)
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Rule:
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Never mix blocking and non-blocking assignment
in a single always block
Non-blocking in registers inferable block
Blocking in combinational block
Simple/easy non-blocking block
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Module Interface
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Example: MUX
/// multiplexer module
module mux4to1x4 (inVec, sel, out);
...
mux4to1 m4_0 (
.vec({in3[0], in2[0], in1[0], in0[0]}),
.sel(sel),
.out(out[0])
);
...
endmodule
Rule:
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Input, Output, InOut
Clock, set/reset, data, address
Use named order
// Module mux4to1 should map to vendor MUX4 cell
module mux4to1 (vec, sel, out);
input [3:0] vec;
input [1:0] sel;
output out;
assign out = vec[sel];
endmodule
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Multiple Assignment
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Never assignment multiple value on one reg/net in
different block
Group similar net/reg together in a block
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Example: Registers (1/2)
Rule:
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module test(clk, load1, a1, load2, a2, q);
input clk, load1, load2, a1, a2;
output q;
reg q;
always @ (posedge clk) begin
if (load1)
q <= a1;
end
always @ (posedge clk) begin
if (load2)
q <= a2;
end
endmodule
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Example: Registers (2/2)
Case over Multiple-if-else
module test(clk, load1, a1, load2, a2, q);
input clk, load1, load2, a1, a2;
output q;
reg q;
always @ (posedge clk) begin
if (load1)
q <= a1;
if (load2)
q <= a2;
end
endmodule
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Rule:
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Rule:
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Always block for state registers update
Always block for next state calculation
Always block for output calculation
Minimize size of state registers
Possible multiple FSM in a module
Parameterize all state encoding
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Each newspaper cost 15 Dollars
Only 10 and 5 Dollars coin
No change
Possible combination: 3x 5 coins, one 10 coin and one 5
coin. Other combinations are not allowable.
Requirements:
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Use "case" instead of multiple nested "if-else if else" block
Newspaper Vending Machine Example
FSM Modeling
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Rule:
Send out control signal for each coin inserted
One output signal which enable newspaper delivery
One reset signal to reset the vending machine
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State Diagram
Machine Diagram
0/0
0/0
5/0
S0
S5
State
10/0
10/0
-/1
S15
5/0
coin
5/0
Combinational
clock
newspaper
reset
S10
10/0
0/0
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FSM Verilog Code
module vend ( coin, clock,
reset, newspaper );
input [1:0] coin;
input clock;
input reset;
output newspaper;
wire newspaper;
wire [1:0] NEXT_STATE;
reg [1:0] PRES_STATE;
reg
fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
//State encoding
parameter
parameter
parameter
parameter
s0 = 2'b00;
s5 = 2'b01;
s10 = 2'b10;
s15 = 2'b11;
//Combination
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FSM Verilog Code (2/2)
always @(PRES_STATE or coin) begin
case (PRES_STATE)
s0: // state = s0
begin
if ( coin ==2'b10) begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end else if ( coin == 2'b01) begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end else begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s0;
end
end
s5: // state = s5
begin
if (coin ==2'b10) begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
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end else if (coin == 2'b01) begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end else begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end
end
s10: // state = s10
begin
if ( fcoin ==2'b10) begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
end else if (coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15;
end else begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
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end
s15: // state = s15
begin
fsm_newspaper = 1'b1;
fsm_NEXT_STATE = s0;
end
default : // state == s0
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s0;
end
endcase
end
assign newspaper = fsm_newspaper;
assign NEXT_STATE = fsm_NEXT_STATE;
//Update State , synchronous reset
always @(posedge clock) begin
if (reset == 1'b1)
PRES_STATE= s0;
else
PRES_STATE = NEXT_STATE;
end
endmodule
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Example 1: FSM k
Example: FSM k
module fsm1a (ds, rd, go, ws,
clk,rst_n);
output ds, rd;
input go, ws;
input clk, rst_n;
parameter [1:0] IDLE = 2'b00,
READ = 2'b01,
DLY = 2'b10,
DONE = 2'b11;
reg [1:0] state, next;
always @(posedge clk or
negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= next;
always @(state or go or ws)
begin
next = 2'bx;
case (state)
IDLE: if (go) next = READ;
else next = IDLE;
READ: next = DLY;
DLY: if (ws) next = READ;
else next = DONE;
DONE: next = IDLE;
endcase
end
assign rd = (state==READ ||
state==DLY);
assign ds = (state==DONE);
endmodule
Possible Glitch on Output!!
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Example 2: FSM k
always @(state or go or ws)
begin
module fsm1 (ds, rd, go, ws,
next = 2'bx;
clk, rst_n);
ds = 1'b0;
output ds, rd;
rd = 1'b0;
input go, ws;
case (state)
input clk, rst_n;
IDLE: if (go) next = READ;
reg ds, rd;
else next = IDLE;
parameter [1:0] IDLE = 2'b00,
READ:
begin rd = 1'b1;
READ = 2'b01,
next = DLY;
DLY = 2'b10,
end
DONE = 2'b11;
DLY: begin rd = 1'b1;
reg [1:0] state, next;
if (ws) next = READ;
always @(posedge clk or
negedge rst_n)
else next = DONE;
if (!rst_n) state <= IDLE;
end
else state <= next;
DONE: begin ds = 1'b1;
next = IDLE;
end
endcase
Possible Glitch on Output!!
end
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endmodule
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Example 3: FSM k (1/2)
module fsm1b (ds, rd, go, ws, clk,
rst_n);
output ds, rd;
input go, ws;
input clk, rst_n;
reg ds, rd;
parameter [1:0]
IDLE = 2'b00,
READ = 2'b01,
DLY = 2'b10,
DONE = 2'b11;
reg [1:0] state, next;
always @(posedge clk or negedge
rst_n)
if (!rst_n) state <= IDLE;
else state <= next;
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always @(state or go or ws)
begin
next = 2'bx;
case (state)
IDLE: if (go) next = READ;
else next = IDLE;
READ: next = DLY;
DLY: if (ws) next = READ;
else next = DONE;
DONE: next = IDLE;
endcase
end
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Example 3: FSM k (2/2)
Example 4: FSM k
module fsm1a_ffo1 (ds, rd, go, ws,
clk, rst_n);
output ds, rd;
input go, ws;
input clk, rst_n;
// state bits = x0 _ ds rd
parameter [2:0]
IDLE = 3'b0_00,
READ = 3'b0_01,
DLY = 3'b1_01,
DONE = 3'b0_10;
reg [2:0] state, next;
always @(posedge clk or negedge
rst_n)
if (!rst_n) state <= IDLE;
else state <= next;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
ds <= 1'b0;
rd <= 1'b0;
end
else begin
ds <= 1'b0;
rd <= 1'b0;
case (state)
IDLE: if (go) rd <= 1'b1;
READ: rd <= 1'b1;
DLY: if (ws) rd <= 1'b1;
else
ds <= 1'b1;
endcase
end
endmodule
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always @(state or go or ws)
begin
next = 2'bx;
case (state)
IDLE: if (go) next = READ;
else next = IDLE;
READ: next = DLY;
DLY: if (ws) next = READ;
else next = DONE;
DONE: next = IDLE;
endcase
end
assign {ds,rd} = state[1:0];
endmodule
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