Verilog Testbench
1
Half Adder Testbench
module halfAdd (sum, cOut, a, b);
output sum, cOut;
i
inputa,
t b;
b
module testAdd ;
wire
sum, cOut;
reg
a, b;
half Add g0(sum, Cout, a, b);
xor
(sum, a, b);
and
(cOut, a, b);
endmodule
initial begin
$monitor ($time
($time,, “a=%b,
“a %b b
b=%b,
%b
sum=%b, cOut=%b”,
a, b, sum, cOut);
a = 0; b = 0;
#10 b = 1;
#10 a = 1;
#10 b = 0;
#10 $finish;
end
endmodule
2
Half Adder Testbench 2
module testAdd2 ;
wire
sum, cOut;
reg
[1:0]
wire
a, b;
assign a = test [0];
assign b = test [1];
test;
half Add g0(sum, Cout, a, b);
initial begin
$monitor ($time
($time,,
“a=%b, b=%b, sum=%b, cOut=%b",
a, b, sum, cOut);
for (test = 0; test < 3; test = test + 1)
#10;
#10
#10 $finish;
end
endmodule
3
Full Adder
module FullAdder(a, b, cin, cout, sum);
i
input
t a, b,
b cin;
i
output cout, sum;
assign { cout, sum } = a + b + cin;
endmdule
4
Full Adder Testbench
module FullAdder_test;
// Signal declaration
reg a, b, cin;
wire cout, sum;
// Instantiate modules
FullAdder g0 (cout,sum,a,b,cin);
// Apply Stimulus
initial
begin
#10 a = 0; b = 0; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 0;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 0;
#10 a = 1; b = 1; cin = 1;
#10 $finish;
endd
//Display results
i iti l
initial
$monitor($time, " a = %b
b = %b cin = %b Cout = %b
S
Sum
= %b"
%b", a,b,c,cin,cout,sum);
b i
)
endmodule
5
Multiplexer Example
PRGXOHPX[WR\GGV
LQSXWGGV
RXWSXW \
RXWSXW\
UHJ \
DOZD\V#GRUGRUV
DOZD\V#G
RU G RU V
EHJLQ
FDVHV
E
E\
G
G
E\ G
HQGFDVH
HQG
G
HQGPRGXOH
6
mux2to1 Testbench
PRGXOHWHVWBPX[WRDQHPSW\SDUDPHWHUOLVWLVXVHG
VLQFHWKLVPRGXOHLVRQO\IRUWHVWLQJ
ZLUH RXW
ZLUHRXW
RXWSXW RI WKH XQLW XQGHU WHVW 887
RXWSXWRIWKHXQLWXQGHUWHVW887
UHJ LQLQVHO
LQSXWVWRWKHXQLWXQGHUWHVW887
,QVWDQWLDWHDQLQVWDQFHRIPX[WR
PX[WR0RXWLQLQVHO
*HQHUDWHWKHWHVWLQJYHFWRUV
LQLWLDOEHJLQRQHWLPHH[HFXWLRQEORFN
LQ E’LQ E’VHO E’
LQ E’
VHO E’
VHO
E’
LQ E’
HQG
HQGPRGXOH
7
Priority Encoder
module priority_encoder_df3 (D, A, V);
input[4:0]
p [
] D;
;
output[2:0] A;
output V;
assign A =D[4] ? 3'b100:
D[3] ? 3'b011:
D[2] ? 3'b010:
D[1] ? 3'b001:
D[0]
[ ] ? 3'b000:
b
3'bxxx;
b
assign V =(D ==5'b00000) ? 1'b0:1'b1;
endmodule
8
Priority Encoder Testbench
`timescale 1 ns / 100 ps //time unit / time precision
module priority_encoder_testbench;
reg clk;
reg[4:0] stim;
wire[3:0] results;
priority_encoder_df3 x1 (stim[4:0], results [3:1], results[0]);
i iti l
initial
begin
clk <= 0;;
stim <= 4’b0;
#330 $stop;
end
9
Priority Encoder Testbench (2)
always
begin
#5
forever
#5 clk
lk <=
< ~clk;
lk
end
always@(posedge clk) begin
stim <= stim + 1;
end
endmodule
10
COUNTER Example
module counter(clk, clear, dout);
input
clk, clear;
output [3:0] dout;
reg [3:0] dout;
always@(posedge
l
@(
d clk
lk or posedge
d clear)
l )
begin
if(clear)
d
dout
<= 4'b000;
b
else
dout <= dout + 1;
end
endmodule
11
COUNTER Testbench
module test_counter;
reg CLOCK, CLEAR;
wire [3:0] Q;
initial
$monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);
counter c1(Q, CLOCK, CLEAR);
iinitial
iti l
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
1 b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
end
12
COUNTER Testbench
initial CLOCK = 1'b0;
always #10 CLOCK = ~CLOCK;
initial
begin
g
#400 $finish;
end
endmodule
13
Inertial versus Transport Delay
• Behavior of Logic Devices Æ inertial delay
a
a_n
• Behavior of Signal Wire Æ transport delay
a_wire
Input to output delay (sometimes “propagation”)
14
Example 1
module mydelay(a1_in, a2_in, b_tran,
b_inertial,
_
c_out);
_ )
input a1_in, a2_in;
output c_out;
output b_tran;
b tran;
wire #2 b_tran;
output b_inertial;
and #3 (b_tran, a1_in, a2_in);
buf #1 (c_out, b_tran);
and #3 (b
(b_inertial,
inertial a1
a1_in,
in a2
a2_in);
in);
endmodule
module test;
wire b_tran, b_inertial, c_out;
wire
i
a1_in,
1 i a2_in;
2 i
reg [1:0] a;
assign a1_in = a[1];
assign
i a2_in
2 i = a[0];
[0]
mydelay g1(a1_in, a2_in, b_tran,
b inertial c_out);
b_inertial,
c out);
initial begin
a = 2'b01;
#2 a = 22'b11;
b11;
#6 a = 2'b10;
#20 $stop;
end
endmodule
15
16
Example 2
module mydelay(a1_in, a2_in, b_tran,
b_inertial,
_
c_out);
_ )
input a1_in, a2_in;
output c_out;
output b_tran;
b tran;
wire #2 b_tran;
output b_inertial;
and #3 (b_tran, a1_in, a2_in);
buf #1 (c_out, b_tran);
and #3 (b
(b_inertial,
inertial a1
a1_in,
in a2
a2_in);
in);
endmodule
module test;
wire b_tran, b_inertial, c_out;
wire
i
a1_in,
1 i a2_in;
2 i
reg [1:0] a;
assign a1_in = a[1];
assign
i a2_in
2 i = a[0];
[0]
mydelay g1(a1_in, a2_in, b_tran,
b inertial c_out);
b_inertial,
c out);
initial begin
a = 2'b01;
#2 a = 22'b11;
b11;
#2 a = 2'b10;
#20 $stop;
end
endmodule
17
18
Gate Delay Model
19
Nonblocking versus Blocking
module block;
reg a, b, c, d, e, f;
initial begin
a = #10 1; // a is assigned at simulation time 10
b = #12 0; // b is assigned at simulation time 22
c = #4 1; // c is assigned at simulation time 26
end
i iti l begin
initial
b i
d <= #10 1; // d is assigned at simulation time 10
e <= #12 0;; // e is assigned
g
at simulation time 12
f <= #4 1; // f is assigned at simulation time 4
end
endmodule
20
module block;
reg a, b, c, d, e, f;
initial begin
#10 a = 1;
// a is assigned at simulation time 10
#12 b = 0;
// b is assigned at simulation time 22
#4 c = 1;
// c is assigned at simulation time 26
end
i iti l begin
initial
b i
#10 d <= 1; // d is assigned at simulation time 10
#12 e <= 0;; // e is assigned
g
at simulation time 22
#4 f <= 1;
// f is assigned at simulation time 26
end
endmodu
21
Display Functions
• $display (and $write)
– $display adds newline, $write does not
– Occurs along with other active events, when encountered
initial #5 $display ("a = %h, b = %b", a, b);
• $strobe
– Similar to $display, but displays data at end of simulation time when
encountered
initial forever @(negedge clock)
$strobe ("Time=%t data=%h", $time, data);
• $monitor
– Displays data at end of current simulation time, whenever a variable in the
argument list changes
initial $monitor ("Time=%t data=%h", $time, data);
22
Display Functions (2)
• $finish causes simulation to stop
• $stopp causes simulation to suspend
p
– Simulation may be resumed
• Formatting string
– %h, %H
hex
– %d, %D
decimal
– %o,
% %O
octal
t l
– %b, %B
binary
– %t
time
• $monitor(“%t: %b %h %h %h %b\n”,
$time, c_out, sum, a, b, c_in);
23
Test Display
module test_display;
reg[3:0] a, b, clk;
initial begin a = 3; b = 2; clk = 1; end
always@(posedge clk) begin
a <= #2 a + b;
#2 b <=
< a - b;
b
$display("display: t = %t, a = %d, b = %d", $time, a, b);
$strobe("strobe: t = %t, a = %d, b = %d", $time, a, b);
endd
initial $monitor("monitor: t = %t, a = %d, b = %d", $time, a, b);
endmodule
24
Display Functions Example [2]
Non-blocking
# monitor:
it t = 0,
0 a = 3,
3 b= 2
# display: t = 2, a = 3, b = 2
# monitor: t = 2, a = 5, b = 1
# strobe: t = 2, a = 5, b = 1
// initialization
i iti li ti
// old values
// new values
// new values
25
Test Display
module test_display;
reg[3:0] a, b, clk;
initial begin a = 3; b = 2; clk = 1; end
always@(posedge clk) begin
a = #2 a + b;
#2 b = a - b;
b
$display("display: t = %t, a = %d, b = %d", $time, a, b);
$strobe("strobe: t = %t, a = %d, b = %d", $time, a, b);
endd
initial $monitor("monitor: t = %t, a = %d, b = %d", $time, a, b);
endmodule
26
Display Functions Example [3]
Blocking
# monitor:
it t = 0,
0 a = 3,
3 b= 2
# monitor: t = 2, a = 5, b = 2
# display: t = 4, a = 5, b = 3
# strobe: t = 4, a = 5, b = 3
# monitor: t = 4, a = 5, b = 3
// initialization
i iti li ti
// a assigned
// new values
// new values
// b assigned
27
assign y = a & b;
assign
g z = y | c;;
initial begin
a = 0; b = 0; c = 0;
#5 a = 0; b = 1; c = 0;
#5 force y = 1;
#5 b = 0;
0
#5 release y;
#5 $stop;
end
assign y = a & b;
assign
i
z = y | c;
initial begin
a = 0;; b = 0;; c = 0;;
#5 a = 0; b = 1; c = 0;
#5 force y = 1;
#5 b = 0;
#5 release y;
#5 $stop;
end
d
28
force/release
assign y = a & b;
g z = y | c;;
assign
initial begin
a = 0; b = 0; c = 0;
#5 a = 0; b = 1; c = 0;
#5 force y = 1;
#5 b = 0;
0
#5 release y;
#5 $stop;
end
T
0
5
10
15
20
a
0
0
0
0
0
b
0
1
1
0
0
c
0
0
0
0
0
y
0
0
1
1
0
z
0
0
1
1
0
29
Simple Microprocessor Datapath
and Control
30
Datapath
1). DFF.v
Help
p Tip:
p
always@(posedge clk)
begin
if(reset)
q <= 0;
else if(ce)
q<= d;
end
d
2). MUX2to1.v
3).
4)
4).
ALU v
ALU.v
5)
5).
MUX4to1.v
DATAPATH v
DATAPATH.v
31
Design Specification
Given the datapath above, design a finite state machine
controller to implement one of the following functions:
(0). R2 = M0 or [ inv(M1) ]
(1). R2 = M0 + M1 + Cin
(2). R2 = M0 + inv(M1) + Cin
(3). R2 = M0 and M1
(4). R2 = M0 nand M1
(5) R2 = M0 or M1
(5).
(6)
(6).
R2 = M0 xor M1
(7). R2 =[ inv(M0)] and M1 (8). R2 = M0 xnor M1
(9) R2 = M0 nor M1
(9).
32
Control
Your finite state machine should generate the
following control signals:
clr, W, S, CE, and sel.
If reset signal is equal to logic ‘1’, your finite state
machine should be in idle state.
Else if start signal is equal to logic ‘1’,
1 , your
finite state machine will start to work.
33
Top Level Design
module top( reset, start, clk, M0, M1, M2, Cin, clr, W, S,
CE, R, Y, sel, A, B );
i
input
reset, start, clk,
lk M0,
M0 M1
M1, M2
M2, Cin;
Ci
output
clr;
output [2:0] W,
W S;
output [3:0] CE, R, Y;
output [1:0] sel;
output
A, B;
……..
endmodule
34
© Copyright 2024 ExpyDoc
