Memory Prof. Stephen A. Edwards [email protected] Columbia University Spring 2011 Memory – p. Early Memories Williams Tube CRT-based random access memory, 1946. Used on the Manchester Mark I. 2048 bits. Memory – p. Early Memories Mercury acoustic delay line. Used in the EDASC, 1947. 32 × 17 bits Memory – p. Early Memories Magnetic core memory, 1952. IBM. Memory – p. Early Memories Magnetic drum memory. 1950s & 60s. Secondary storage. Memory – p. Modern Memory Choices Family Programmed Persistence Mask ROM at fabrication ∞ PROM once ∞ EPROM 1000s, UV 10 years FLASH 1000s, block 10 years EEPROM 1000s, byte 10 years NVRAM ∞ 5 years SRAM ∞ while powered DRAM ∞ 64 ms Memory – p. ROMs Memory – p. EPROMs Memory – p. EEPROM and FLASH Slow write Oxide floating gate Word Line Source Drain Channel (bit line) FowlerNordheim Tunneling EEPROM: bit at a time FLASH: block at a time Source: SST Memory – p. Static RAM Cell Word Bit Bit Memory – p. 1 Standard SRAM: 6264 19–15,13–11 D[7:0] 10–2,25–23,21 22 27 20 26 Addr[12:0] OE WE CS1 CS2 8K × 8 Can be very fast: Cypress sells a 55ns version Simple, asynchronous interface Memory – p. 1 Standard SRAM: 6264 CS1 ÀÀÀ ÄÄÄÄÄ¡ÀÀÀ ÄÄÄÄÄ¡ÀÀÀ CS2 ÄÄÄ¡ÀÀÀÀÀ ÄÄÄ¡ÀÀÀÀÀ ÄÄÄ WE ÀÀÀÀ ÄÄÄ¡ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ OE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ ÄÄ¡ÀÀÀÀ Addr ÍÍ§ÎÎÎÎÎÎÎ¦ÍÍÍ§ÎÎÎÎ¦ÍÍÍ Data ¢ÎÎÎÎÎÎÎÎ£ ¢ÎÎ£ Memory – p. 1 byanacti LOW (CE anactiveHIGH enab and LOW output e able ( )a e drivers. d vices h ve an a omatic power-down f ure ( cing p b Standard SRAM: 6264 Theinpu /outputpinsremai ahigh-i ec s outputs are ena GH. Adie coat is k Co I/O0 INPUTBUFFER A1 A2 A3 A4 A5 A6 A7 A8 I/O1 I/O2 I/O3 256x32x8 ARRAY GN I/O4 I/O5 I/O6 CE1 CE2 WE COLUMNDECODER POWER DOWN I/O7 OE CY6264-1 Memory – p. 1 Toshiba TC55V16256J 256K × 16 38–35,32–29,16–13,10–7 D[15:0] 23,22,18–21,24–27,42–44,1–5 40 39 41 17 6 Addr[17:0] UB LB OE WE CE 12 or 15 ns access time Asynchronous interface UB, LB select bytes Memory – p. 1 Toshiba TC55V16256J 256K × 16 Memory – p. 1 Dynamic RAM Cell Row Column Basic problem: Leakage Solution: Refresh Memory – p. 1 Ancient DRAM: 4164 64K × 1 Apple IIe vintage 9,13,10–12,6,7,5 2 3 15 4 Addr[7:0] 14 DIN DOUT WE CAS RAS Memory – p. 1 Basic DRAM read and write cycles RAS ÀÀ ÄÄÄÄÄÄÄÄÄ¡ÀÀ ÄÄÄÄÄÄ¡ÀÀ CAS ÀÀÀÀÀÀ ÄÄÄÄÄ¡ÀÀÀÀÀÀ ÄÄ¡ÀÀ Addr §ÎÎ¬ÎÎ¦ÍÍÍÍÍ§ÎÎ¬ÎÎ¦ÍÍÍÍ WE Din Dout Row Row Col ÆÀÀ¯ Col ÄÄ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ§ÎÎ¦ÍÍÍ ¢ÎÎÎ£ Memory – p. 1 Page mode read cycle RAS ÀÀ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¡À CAS ÀÀÀÀÀÀ ÄÄÄ¡À ÄÄÄ¡À ÄÄ¡À Addr §ÎÎ¬ÎÎ¦ÍÍÍ§ÎÎ¦Í§ÎÎ¦ÍÍÍ WE Din Dout Row Col Col Col ÆÀÀÀ¯ ÆÀÀÀ¯ÆÀÀÀÀ¯ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ¢ÎÎÎ£ ¢ÎÎÎ£ ¢ÎÎÎ Memory – p. 1 Samsung 8M × 16 SDRAM 21,20 39 15 3 15 15 37 38 BA[1:0] Addr[11:0] DQ[15:0] UDQM LDQM WE CAS RAS CKE CLK Bank address Address (multiplexed) Data I/O Upper byte enable Lower byte enable Write enable Column Address Strobe Row Address Strobe Clock Enable Clock Synchronous interface Designed for burst-mode operation Four separate banks; pipelined operation Memory – p. 2 Samsung 8M × 16 SDRAM I/O Control Data Input Register LWE LDQM Bank Select 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Output Buffer 8M x 4 / 4M x 8 / 2M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 8M x 4 / 4M x 8 / 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM Memory – p. 2 SDRAM: Control Signals RAS CAS WE action 1 1 1 NOP 0 0 0 Load mode register 0 1 1 Active (select row) 1 0 1 Read (select column, start burst) 1 0 0 Write (select column, start burst) 1 1 0 Terminate Burst 0 1 0 Precharge (deselect row) 0 0 1 Auto Refresh Mode register: selects 1/2/4/8-word bursts, CAS latency, burst on write Memory – p. 2 SDRAM: Timing with 2-word bursts Load Active Write Read Refresh Clk Ä¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ RAS ¡ÀÀÀÀ ¡ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ ¡À CAS ¡ÀÀÀÀÀÀÀÀÀÀÀÀ ¡ÀÀÀÀ ¡ÀÀÀÀÀÀÀÀÀÀÀÀ ¡À WE ¡ÀÀÀÀÀÀÀÀÀÀÀÀ ¡ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ Addr §¦ÍÍÍÍ§¦ÍÍÍÍ§¦ÍÍÍÍ§¦ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ BA ÍÍÍÍÍÍÍÍ§¦ÍÍÍÍ§¦ÍÍÍÍ§¦ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ DQ Op R B C C B B ¢¦§£ W W ¢£¢£ R R Memory – p. 2