High Performance p-type SnO thin-film Transistor with SiOx

http://dx.doi.org/10.5573/JSTS.2014.14.5.666
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
High Performance p-type SnO thin-film Transistor with
SiOx Gate Insulator Deposited by Low-Temperature
PECVD Method
Myeonghun U1, Young-Joon Han1, Sang-Hun Song1, In-Tak Cho2, Jong-Ho Lee2,
and Hyuck-In Kwon1,*
Abstract—We have investigated the gate insulator
effects on the electrical performance of p-type tin
monoxide (SnO) thin-film transistors (TFTs). Various
SnO TFTs are fabricated with different gate
insulators of a thermal SiO2, a plasma-enhanced
chemical vapor deposition (PECVD) SiNx, a 150 oCdeposited PEVCD SiOx, and a 300 oC-deposited
PECVD SiOx. Among the devices, the one with the
150oC-deposited PEVCD SiOx exhibits the best
electrical performance including a high field-effect
mobility (=4.86 cm2/Vs), a small subthreshold swing
(=0.7 V/decade), and a turn-on voltage around 0 (V).
Based on the X-ray diffraction data and the localizedtrap-states model, the reduced carrier concentration
and the increased carrier mobility due to the small
grain size of the SnO thin-film are considered as
possible mechanisms, resulting in its high electrical
performance.
Index Terms—P-type SnO TFTs, gate insulator,
PECVD SiOx, localized-trap-states model
I. INTRODUCTION
Oxide semiconductor-based thin-film transistors
(TFTs) have attracted considerable attention due to their
Manuscript received Jun. 12, 2014; accepted Aug. 11, 2014
1
School of Electrical and Electronics Engineering, Chung-Ang
University, Seoul 156-756, Korea
2
Department of Electrical and Computer Engineering, Seoul National
University, Seoul 151-742, Korea
E-mail : [email protected]
excellent electrical performances. [1] However,
compared to the n-type oxide TFTs including zinc oxide
(ZnO) and amorphous indium-gallium-zinc oxide (aIGZO) TFTs, the p-type oxide TFTs have suffered from
the low hole mobility, which has prevented the
implementation of complementary logic-based circuits
with the n-type oxide TFTs. Since the work from Ogo et
al. in 2008 [2], tin monoxide (SnO) has attracted special
attention as a channel material of the p-type oxide TFT
due to the possibility for high hole mobilities, and
various research results have been reported about the
SnO-based p-type oxide TFTs. Liang et al. [3]
investigated the effects of vacuum annealing on the
electrical performance of SnO TFTs, and Okamura et al.
[4] reported the SnO TFT fabricated using the solution
process. Recently, Frescas et al. [5] tried to optimize the
oxygen partial pressure and total pressure during the
channel deposition by DC magnetron sputtering, and
successfully demonstrated the record high mobility (~
6.75 cm2/Vs) for p-type SnO TFTs on glass substrates.
Various dielectrics including Al2Ox, thermal SiO2, and
HfO2 were used as gate insulators of SnO TFTs [2-6].
However, as of yet, no comparative report has been made
on the effects of gate insulator in p-type SnO TFTs
although the gate insulator can strongly affect the
electrical performance of field-effect transistors
including TFTs [7]. In this article, for the first time to the
best of our knowledge, we comparatively investigate the
effects of gate insulators on the electrical performance of
p-type SnO TFTs. The experimental results show that it
is very important to optimize the gate insulator to
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
667
improve the electrical performance in p-type SnO TFTs.
II. EXPERIMENTS
The experiments were performed on the p-type bottom
gate SnO TFTs, where a heavily doped n-type silicon
wafer was used as a substrate and a gate electrode. Four
different dielectric layers including a thermal SiO2 (= 116
nm), a SiNx (= 110 nm) deposited by plasma-enhanced
chemical vapor deposition (PECVD) at 250oC, and two
SiOxs deposited by PECVD at 150 (= 113 nm) and 300oC (=
99 nm) were incorporated into the devices as gate
insulators. A thermal SiO2 was grown by dry oxidation at
1000oC, and two SiOx layers were formed in different
commercial foundries under different deposition
conditions, respectively. After the formation of gate
insulators, a 10 nm-thick SnO thin-film was deposited
onto the insulator/Si substrates by RF magnetron
sputtering with a 3 '' diameter metallic Sn target. The
sputtering condition is as follows: a RF power of 50 W, a
working pressure of 3 mTorr, a substrate temperature of
90oC, a substrate-to-target distance of 140 mm, and a gas
(Ar + O2) mixing ratio of Ar/O2 = 90/6 (sccm/sccm). For
the source/drain electrodes, a 50-nm-thick Ni was
deposited at RT using an e-gun evaporator. All the layers
in this work were patterned using shadow masks. The
dielectric constants of the gate insulators are extracted to
be 3.8, 8.7, 8.3, and 6.5 for a thermal SiO2, a PECVD
SiNx, a 150oC-deposited PEVCD SiOx, and a 300oCdeposited PECVD SiOx, respectively. The relatively high
dielectric constants of PEVCD SiOxs are believed to be
caused from the hydroxyl group inside the PEVCD SiOx
[8]. The hydroxyl group in the PECVD SiOx has been
known to increase the dielectric constant of the PECVD
SiOx, and the low-temperature deposited PECVD SiOx
can have more hydroxyl group due to the silanol and
water impurities contained in the SiOx [9].
III. RESULTS AND DISCUSSION
Fig. 1(a) shows the representative transfer curve of the
p-type SnO TFTs fabricated with a 150oC-deposited
PECVD SiOx gate insulator. Measurements were made
for a device with a channel width/length (W/L) of 1000
μm/50 μm at a drain-to-source voltage (VDS) of -2 V. The
curve clearly exhibits the p-type behavior with a field-
Fig. 1. Representative (a) transfer, (b) output characteristics of
the p-type SnO TFTs fabricated with a 150oC-deposited
PECVD SiOx gate insulator.
effect mobility (μFE) of 4.86 cm2/Vs, a subthreshold
swing (SS) of 0.7 V/decade, a threshold voltage (Vth) of 2.3 V, a turn-on voltage (Von) of -0.1 V, and a current
on/off ratio (Ion/off) of ~ 3 × 104, where μFE was
determined by the maximum transconductance at a VDS
of -2.0 V [10], and Vth was estimated by the intercept of
the extrapolated curve with a voltage axis. When
compared with p-type SnO TFTs reported in previous
works, the extracted μFE is the second largest value, after
that of the record mobility device fabricated by Frescas et
al. [5], however, our device exhibits much steeper SS and
a more negatively shifted Von compared to the device of
Frescas et al. [5]. Fig. 1(b) depicts the representative
output curves of the fabricated TFTs using a 150oCdeposited PECVD SiOx gate insulator, which exhibit a
clear pinch-off and a current saturation.
Fig. 2 compares the transfer curves and gate leakage
currents of the p-type SnO TFTs fabricated using various
gate insulators. It shows that the devices with different
gate insulators exhibit much different transfer curves,
which implies that the electrical performance of p-type
SnO TFT strongly depends on the gate insulator. As
shown in Fig. 1(a), the transfer curve of the SnO TFT
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MYEONGHUN U et al : HIGH PERFORMANCE P-TYPE SNO THIN-FILM TRANSISTOR WITH SIOX GATE INSULATOR …
Fig. 2. Transfer curves and gate leakage currents of the p-type
SnO TFTs fabricated using various gate insulators of a thermal
SiO2, a PECVD SiNx, a 150oC-deposited PEVCD SiOx, and a
300oC-deposited PECVD SiOx.
fabricated using a 150oC-deposited PECVD SiOx shows
a small SS, a Von around 0 (V), and a relatively high Ion.
However, the devices fabricated using different gate
insulators of a thermal SiO2, a PECVD SiNx, and a
300oC-deposited PECVD SiOx exhibit a much larger SS,
a more positively shifted Von, and a relatively lower Ion
compared to the device with a 150oC-deposited PECVD
SiOx even though the SnO channel layer is deposited
under the same conditions in all devices. Fig. 2 also
shows that the gate leakage currents of the device with a
150oC-deposited PECVD SiOx exhibit relatively larger
values than those of the devices with other gate insulators.
To investigate the physical and chemical mechanism
of the observed phenomenon in Fig. 2, we compare the
X-ray diffraction (XRD) patterns of 10 nm-thick SnO
thin-films deposited on various gate insulators (Fig. 3).
In Fig. 3, the crystalline peaks corresponding to the (001),
(101), (002), (112), and (103) directions of the SnO
phase are clearly observed in the XRD patterns of SnO
thin-films deposited on a thermal SiO2 and a PECVD
SiNx gate insulators. However, only a small and broad
peak corresponding to the (101) direction of the SnO
phase is observed in a XRD pattern of the SnO thin-film
deposited on a 150oC-deposited PECVD SiOx gate
insulator, which implies that the SnO thin-film on a
150oC-deposited PECVD SiOx gate insulator has a small
grain size and a low crystallinity. The XRD pattern of the
SnO thin-film on a 300oC-deposited PECVD SiOx gate
insulator exhibits a SnO (101) peak larger than that in the
Fig. 3. XRD patterns of 10 nm-thick SnO thin-films deposited
on various gate insulators of a thermal SiO2, a PECVD SiNx, a
150oC-deposited PEVCD SiOx, and a 300oC-deposited PECVD
SiOx.
XRD pattern of the thin-film on a 150oC-deposited
PECVD SiOx gate insulator.
From the XRD data in Fig. 3, a plausible mechanism
which can explain the results in Fig. 2 can be suggested
based on the Seto’s localized-trap-states model [11].
Generally, the small grain size of the polycrystalline thinfilm has been known to decrease the carrier mobility due
to the increased number of grain boundaries. However,
several papers regarding the polycrystalline silicon thinfilm [12] and pentacene-based organic TFTs [13]
reported the opposite trend between mobility and grain
size (increasing mobility with a decreasing grain size),
and this inconsistency has been explained based on the
Seto’s localized-trap-states model. The localized-trapstates model correlates the grain size of the
polycrystalline thin-film with the carrier concentration
and carrier mobility based on the assumption that
crystallites of the polycrystalline thin-films have very
low trap state density inside the grain, and that most trap
states are localized at the grain boundary. Figs. 4(a)-(c)
schematically show the variation of the trap density and
the resulting band diagram with respect to the grain size
in polycrystalline p-type semiconductor materials [11,
12]. Here, Nt is the trap density per area, L is the average
grain size, n is the carrier (hole) concentration, and Eb is
the potential barrier height at the grain boundary.
In the localized-trap-states model, the small grain size
reduces the free carrier concentration inside the
polycrystalline semiconductor thin-film, because the free
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
Fig. 4. Schematic diagram of localized-trap-states model and
corresponding band structure in polycrystalline p-type
semiconductor materials. Along with the grain size, the band
structure varies from (a) to (c).
carriers are trapped by the localized trap states at grain
boundaries. Moreover, when a number of trap states per
unit volume is larger than the free carrier concentration
due to the large number of grain boundaries, the trap
states are not completely filled by free carriers, which
reduces the potential barrier height at the grain
boundaries as depicted in Fig. 4(a) and increases the
carrier mobility inside the polycrystalline thin-films due
to the reduced grain boundary scattering [12]. As well
known, a reduced carrier concentration inside the thinfilm enhances the current modulation by the gate voltage
in TFTs, and moves Von to the negative direction in ptype TFTs. In Fig. 2, the p-type SnO TFT fabricated
using a 150oC-deposited PECVD SiOx exhibits a higher
μFE, a smaller SS, and a negatively shifted Von compared
to the devices with a thermal SiO2 and a PECVD SiNx
gate insulators. Considering a small and broad peak in
the XRD pattern of the SnO thin-film deposited on a
150oC-deposited PECVD SiOx gate insulator in Fig. 3,
the results in Fig. 2 is well explained by the localizedtrap-states model. We made Hall measurements to
investigate the electrical properties of SnO thin-films on
different gate insulators, but good Hall data were not
available due to the low conductivities in all samples.
Fig. 5 shows the atomic force microscopy (AFM)
images for different gate insulators deposited on a
heavily doped n-type silicon wafer. It shows that a
150oC-deposited PECVD SiOx gate insulator exhibits the
largest root mean square (RMS) roughness among
various gate insulators. From the previous work [14], a
roughening transition temperature of PECVD SiOx was
reported as ~ 250oC. Above this temperature, the SiOx
669
Fig. 5. AFM images for different gate insulators of (a) a
thermal SiO2 (= 116 nm), (b) a PECVD SiNx (= 110 nm), (c) a
150oC-deposited PEVCD SiOx (= 113 nm), (d) a 300oCdeposited PECVD SiOx (= 99 nm) deposited on a heavily
doped n-type silicon wafer.
thin-film is dense and smooth, but below this was
reported as ~ 250oC. Above this temperature, the SiOx
thin-film is dense and smooth, but below this deposition
temperature, the SiOx thin-film becomes porous and
rough. The rough surface of 150oC-deposited PECVD
SiOx in Fig. 5 and the relatively large gate leakage
current of the device with a 150oC-deposited PECVD
SiOx gate insulator in Fig. 2 are consistent with the report
in the previous work. The increased surface roughness of
the gate insulator can decrease the grain size of the thinfilm, because it reduces the energy barrier for nucleation
during the formation of the nuclei [15]. The smallest
grain size deduced from the XRD data in a SnO thin-film
on a 150oC-deposited PECVD SiOx gate insulator is
believed to be caused from the roughest surface of a
150oC-deposited PECVD SiOx gate insulator.
IV. CONCLUSIONS
In this article, we examine the effects of gate insulators
on the electrical performance of p-type SnO TFTs.
Various SnO TFTs are fabricated with different gate
insulators of a thermal SiO2, a PECVD SiNx, a 150oCdeposited PEVCD SiOx, and a 300oC-deposited PECVD
SiOx, and the device fabricated with a 150oC-deposited
PEVCD SiOx exhibits a much higher μFE, a smaller SS,
and a more negatively shifted Von compared to the
devices with other gate insulators. From the XRD data,
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MYEONGHUN U et al : HIGH PERFORMANCE P-TYPE SNO THIN-FILM TRANSISTOR WITH SIOX GATE INSULATOR …
the peaks corresponding to the crystalline SnO phase are
clearly observed in the SnO thin-films on a thermal SiO2
and a PECVD SiNx gate insulators, but only a small and
broad peak corresponding to the (101) direction of the
SnO phase is observed in the SnO thin-film deposited on
a 150oC-deposited PECVD SiOx gate insulator. It implies
that the SnO thin-film on a 150oC-deposited PECVD
SiOx gate insulator has a small grain size and a low
crystallinity. Based on the localized-trap-states model,
the reduced carrier concentration and the increased
carrier mobility due to the small grain size of the SnO
thin-film are considered as plausible mechanisms
resulting in the high electrical performance of the p-type
SnO TFT fabricated with a 150oC-deposited PECVD
SiOx gate insulator.
ACKNOWLEDGMENTS
This research was supported by the National Research
Foundation of Korea(NRF) grant funded by the Korea
government(MSIP) (No. 2014-005368) and by the ChungAng University Research Scholarship Grants in 2013.
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
Myeonghun U received a bachelor’s
degree in physics from Dongguk
University, Seoul, Korea in 2012. He
is currently a graduate school student
in the School of Electrical and
Electronics Engineering at ChungAng University in Seoul. His current
research interests include oxide thin-film transistors.
Young-Joon Han received a
bachelor’s degree in Electrical and
Electronics Engineering from ChungAng University, in 2013. He is
currently a graduate school student in
the School of Electrical and Electronics Engineering at Chung-Ang University in Seoul.
His current research interests include Fabrication of ptype SnO Thin-Film Transistors.
Sang-Hun Song received his BS
degree in Electronics Engineering from
Seoul National University in 1986 and
his MA and Ph.D. degrees both from
Princeton University in 1988 and 1997
respectively. His doctoral research
studied on magneto optical and
magneto transport properties of the 2 dimentional carriers in
strained semiconductor layers. In 1997, he joined LG
Semincon Co., Ltd. as a DRAM circuit designer. In 2001, he
joined the School of Electrical and Electronics Engineering
at Chung-Ang University in Seoul, where he is now a
professor. In 2007, he was a visiting scholar to GLAM at
Stanford University. His research interests include
semiconductor physics and devices, memory devices,
nanoelectronics and novel techniques in semiconductor
characterization. Recently, he is working on sensors that can
detect force and mass.
671
In-Tak Cho received B.S and M.S
degrees in electrical engineering from
Kyungpook National University, Seoul,
Korea in 2008 and 2010, respectively.
He is currently working toward the
Ph.D. degree in electrical engineering
at Seoul National University, Seoul,
Korea. His research interest is metal oxide semiconductor TFT and TMDC FET.
Jong-Ho Lee received the Ph.D.
degree from Seoul National University,
Seoul, in 1993, in electronic
engineering. In 1994, he was with
the School of Electrical Engineering,
Wonkwang
University,
Iksan,
Chonpuk, Korea. In 2002, he moved
to Kyungpook National University, Daegu Korea, as a
Professor of the School of Electrical Engineering and
Computer Science. Since September 2009, he has been a
Professor in the School of Electrical Engineering, Seoul
National University, Seoul Korea. From August 1998 to
July 1999, he was with Massachusetts Institute of
Technology, Cambridge, as a postdoctoral fellow. He has
authored or coauthored more than 160 papers published
in refereed journals and over 280 conference papers
related to his research and has been granted ~90 patents
in this area. His research interests include CMOS
technology, non-volatile memory devices, thin film
transistors, sensors, bio interface, and neuromorphic
technology. He has been served as a subcommittee
member of IEDM, ITRS ERD member, a general chair of
IPFA2011, and IEEE EDS Korea chapter chair. In 2006,
he was a recipient of the “This Month’s Scientist Award”
for his contribution in the development of practical highdensity/high-performance 3-dimensional nano-scale
CMOS devices. He invented Saddle FinFET (or recess
FinFET) for DRAM cell and NAND flash cell string with
virtual source/drain, which have been applying for mass
production.
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MYEONGHUN U et al : HIGH PERFORMANCE P-TYPE SNO THIN-FILM TRANSISTOR WITH SIOX GATE INSULATOR …
Hyuck-In Kwon received the B.S.,
M.S., and Ph.D. degrees in electrical
engineering from Seoul National
University, Seoul, in 1999, 2001, and
2005, respectively. From August
2004 to March 2006, he was a
Research
Associate
with
the
University of Illinois, Urbana. In 2006, he joined the
System LSI Division, Samsung Electronics Company,
Korea, where he was a Senior Engineer with the Image
Development Team. From September 2007 to February
2010, he worked for the School of Electronic
Engineering in Daegu University as a Full-Time Lecturer
and an assistant professor. Since 2010, he has been with
Chung-Ang University, Seoul, Korea, where he is
currently an associate professor in the School of
Electrical and Electronics Engineering. His research
interests include CMOS active pixel image sensors,
oxide thin-film transistors, GaN-based power devices,
and silicon nanotechnologies.

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