IBM PDK PCell Development Flow and Evaluation of OpenPDK

IBM PDK PCell Development Flow
and Evaluation of OpenPDK
Sue Strang
DAC 2014
Moscone Center, San Francisco
DAC 2014
IBM Corporation
Agenda
 IBM Foundry Offerings
 Evolution of IBM Technology and PDK/PCell Challenges
 Technology Phases and the PCell requirements
 PCell Development and Test Flow
 OpenPDK for IBM’s PCell Development Methodology
IBM Confidential
2
IBM Semiconductor Foundry
Burlington, VT - 200mm
Fishkill, NY - 300mm
Albany Nanotech – Advanced Nodes
3 DAC 2014
IBM Corporation
PDK Challenges in IBM Technologies
1990
Foundry
Offering with
Vendor Tools
Adv 2014
300mm
200mm
Global/Local
Density
High Voltage
Devices NVRAM
Optimal Proximity Correction
Scaling
Retargetting
FinFET
LLE
On chip ESD
Multi-chip Modules & 3DIC
Restricted DesignRules
Contacted Poly Pitch
Millimeter Wave
Inductor Synthesis
Photonics
Engineered Stress
Silicon On Insulator
500nm
250nm
130 nm
grid1
grid2
DFM/YCD
Double Patterning
Industry-leading eDRAM
90 nm
65 nm
45 nm
32 nm
Triple Patterning
Unidirectional
Wiring
20 nm
14 nm
Imaging
10 nm
7 nm
180 nm
4 DAC 2014
IBM Corporation
Technology Phases and PCell requirements
Technology Phase
Technology Demonstration
PCell Requirements
Testing Requirements
FEOL MOL BEOL structures shape
variations
electrical characteristic meas
Limited design rule definition
Device Design
Design Rule Validation
Experimental Devices
Parameter variability
Design Rule structures
Design rule aware
Allow design rule extension
Limited features, design rules
Memory Design
Logic Library
Early Adopter Designs
Model correlation
Routing features
Design, process constraints
Feature testing
Parameter range testing
IP testing
Foundry Offering
General Availability
Parameter limitation
Release Migration
DFM Features
Full quality testing
Parameter limits
Model correlation
Process Variants
PCell compatibility
PCell variations per tech
Full quality testing
Backward compatibility
5 DAC 2014
IBM Corporation
PCell Development Flow
Specifications
dita
Design Manual
Development
Testing
Device Models
Techfile
Automated Tests
Device Specification
Manual Tests
LVS
Model Specification
Parameter Attributes
Netlist
Device Information
DRC
DDF Container
IP Tests
LVS Specification
PCells
Test Specification
Parameter Attributes
Hierarchical structures
Symbols, Layouts
IP
Device input information in several formats!
6 DAC 2014
IBM Corporation
OpenPDK for PCells
OpenPDK PCell
Source Code
Open
Community
XML Parser
Owned by Si2
XML based on XSD
Foundry/
Vendor
Proprietary
DDF
Tools
Interface
Design Manual
LVS Spec
Device Spec
Model Spec
Test Spec
Test Spec
7 DAC 2014
Vendor X
Code Block
Vendor Y
Code Block
Vendor Z
Code Block
IBM Corporation
IBM Evaluation of OpenPDK for PCells
IBM PCells
DEMO045
mos.pcell.il
mos.cdf.il
Si2 Standard
Device
Representation
Schemas (XSD)
(XML)
Using the syntax
setup by
Symbols
Callbacks
Parameters
res.pcell.il
res.cdf.il
8 DAC 2014
To create
SPICE Netlist
PCell code
Next steps
Import into PDK
Validate PCell
IBM Corporation
IBM Perspective on OpenPDK PCells
OpenPDK Advantages for PCell develoment:
Standardized technology and device information leads to better syncing of design and manufacturing.
OpenPDK will utilize code blocks directly from Vendor language for ease of adoption (300mm).
The Common Grammar Language utilized for implementations in multiple EDA vendor tools (200mm).
OpenPDK well-aligned with goals of Design Enablement and Design Manual automation.
An OpenPDK specification syncs technology information to/from IBM partners.
OpenPDK Challenges for PCell develoment:
Import of device information into XML format is manual.
Advanced technology nodes require features not yet defined in standard.
Multiple vendor implementation increases test matrix.
Need to evaluate Methodology flow for multiple PCell implementations
9 DAC 2014
IBM Corporation
10 DAC 2014
IBM Corporation

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