Spansion Embedded NAND NAND Flash Basics 1 © 2012 Spansion, Inc. CONFIDENTIAL NOR vs. NAND Flash – Structure BL SSL WL0 WL1 WL2 Control Gate WL13 WL14 WL15 DSL Floating Gate Drain Source Source Drain Bit line Contact (DRC) Source DSL (Drain Sel. Line) WL1 WL (Control Gate) WL2 Floating Gate WL3 WL4 SSL (Source Sel. Line) Source Bit line Cell Source Line NAND Cell 2 © 2012 Spansion, Inc. NOR Cell CONFIDENTIAL Drain NAND Flash Organization 3 © 2012 Spansion, Inc. CONFIDENTIAL Concept of NAND Cell 1) NAND Flash Cell 2) MOS Transistor Control gate Gate Floating gate Source P-well Drain VS Source P-well Drain NAND flash as a solid-state memory device Each memory cell represent its “zero” or “one” state, which is identified by means of amount of trapped electrons in the floating gate. 4 © 2012 Spansion, Inc. CONFIDENTIAL NAND Operation - Read 0V 0V Control gate Control gate Floating gate Floating gate Drain Source Drain Source Current P-well Current P-well Programmed Cell, bit data= “Zero” Erased Cell, bit data= “One” Read Operation in a programmed cell Read Operation in an erased cell How to judge whether a bit data is ‘0’ or ‘1’ from a NAND cell Control gate is biased as judging voltage(0V) and then If current can’t flow from Drain to Source, the NAND cell is programmed (bit data ‘1’). If current can flow from Drain to Source, the NAND cell is erased (bit data ‘0’). 5 © 2012 Spansion, Inc. CONFIDENTIAL NAND Operation - Program 18V Number of bits Control gate Erase cell Floating gate ‘1’ Drain Source Program cell P-well 0V ‘0’ Vth (Threshold Voltage) Program Operation, bit data= “Zero” Vth Shift by Program Operation NAND Cell Program Operation • In order to program the cell transistor, a high voltage (e.g. 18V) is applied to its control gate and a ground voltage is applied to its drain and substrate. • Under this bias condition, electrons in the substrate are injected into the floating gate by F-N tunneling effect. • The threshold voltage of programmed cell shifts into positive direction (e.g. 1V or higher). • This state is defined as data “zero” and a flash memory cell having the data “zero” a state is called an “off-cell”. 6 © 2012 Spansion, Inc. CONFIDENTIAL NAND Operation - Erase 0V Number of bits Control gate Erase cell Floating gate ‘1’ Drain Source P-well 20V Program cell ‘0’ Vth (Threshold Voltage) Erase Operation, bit data= “One” Vth Shift by Erase Operation NAND Flash Cell Erase Operation • A cell transistor erase is carried out by applying a ground voltage to its control gate and a voltage (e.g. 20V) to its substrate. • This large voltage difference sets up a strong electric field between the floating gate and the substrate such that electrons on the floating gate are discharged into the substrate. • A threshold voltage of erased cell transistor shifts into a negative direction (e.g. -3V). This state is defined as data “one” and the state is called an “on-cell”. 7 © 2012 Spansion, Inc. CONFIDENTIAL www.spansion.com Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™ and combinations thereof are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. This document is for informational purposes only and subject to change without notice. Spansion does not represent that it is complete, accurate or up-to-date; it is provided “AS IS.” To the maximum extent permitted by law, Spansion disclaims any liability for loss or damages arising from use of or reliance on this document. 8 © 2012 Spansion, Inc. CONFIDENTIAL
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