pdf file

Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Polytech’Montpellier – MEA4
M2 EEA – Systèmes Microélectroniques
Analog IC Design
Building a DC Small-Signal Model of a CMOS Analog Circuit:
a comprehensive guide
Pascal Nouet – 2014/2015 - [email protected]
http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html
Objective / Content
•  Demystify the building of a low-frequency (dc)
small-signal model for your CMOS analog circuit
•  A step by step straightforward approach
•  Pre-requisites
–  Good practice of solving electrical circuits (Node and
Mesh laws)
–  Large- and small-signal models for MOST in stronginversion
•  Content
–  A comprehensive guide
–  A set of exercises
•  Next step
–  Solving small-signal circuits
1
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
From Norton (Current) Source to
MOS transistor
Practical Current Source ≠ Current supply
Ideal
Current supply
Norton Source
MOST DrainSource Current
(Model)
(e.g. "idc" within simulator)
I
I
I
I
I
V
r0
V
r0
V
V
I
Norton
V
V
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
2
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Large-signal model of the MOS
transistor: saturation current, Idsat
Ids
I dsat =
µnCox W 2
Veff = 3.6 µA
2 L
Vgs = 0.6 V
Value of µ.Cox ?
NMOS W=10µm and L=2µm
Veff = 100mV
Vds (V)
Small-signal model of the MOS
transistor: transconductance, gm
Ids
Vgs = 0.61 V
Vgs = 0.6 V
0.6 µA
0.6 µA
Vgs = 0.59 V
∂I dsat
W
= µCox Veff = gm
L
∂Vgs
⇒ gm =
2 ⋅ I dsat
W
= 2 µCox I dsat
L
Veff
Vds (V)
3
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Small-signal model of the MOS
transistor: output resistance, rds
Ids
I dsat =
µnCox W 2
Veff = 3.6 µA
2 L
I ds = I dsat !"1+ λn ( Vds -Veff )#$
Vgs = 0.6 V
ΔIds / ΔVds = 0,145 µA/V
ΔI ds
λn =
Veff = 100mV
ΔVds
≅ 4.10 −2 V −1
I dsat
Value of λ for this NMOST ?
Vds (V)
Pre-requisite summary
•  N-type MOS transistor
SSM in strong inversion
–  3 independent terminals
d1
g1
g1
d1
gm1vgs1
T1
s1
g2, d2
s2
s3
s3
rds1
g3
gm3vgs3
T3
d3
rds3
g3
d3
–  2-terminal (diode-like)
s4
1
gm2
T2
s2
–  3 independent terminals
s1
–  2-terminal (diode-like)
g2, d2
•  P-type MOS transistor
SSM in strong inversion
g4, d4
1
gm 4
T4
g4, d4
s4
4
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
Characterization of a diodeconnected NMOS Transistor
Ids (A)
I dsat =
µn Cox W
Veff 2
2 L
Vgs
Vds & Vgs (V)
5
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Characterization of a diodeconnected NMOS Transistor
Veff (V)
0.5
1
2
Idsat (µA)
171
647
2380
δIds/δVgs
(mA/V)
0.709
1.28
2.23
µnCox (A/V2)
1.42e-4
1.28e-4
1.12e-4
µnCox (A/V2)
1.37e-4
1.29e-4
1.19e-4
gm =
∂I ds
g
W
= µnCox Veff ⇒ µnCox = m
W
∂Vgs
L
Veff
L
&W 2 #
µnCox = 2 I dsat $ Veff !
"
%L
µn.Cox = 112 to 142 µA/V2
Characterization of a diodeconnected NMOS Transistor
45
40
35
Average : 126 µA/V2
µnCox (µA/V2)
Standard-deviation : 24 µA/V2
30
25
20
15
10
5
0
6
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Characterization of rds (PMOS)
1.E+10
1.E+09
rds (Ω
Ω)
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.00E-‐01
1.00E+00
1.00E+01
Idsat (µA)
1.00E+02
1.00E+03
Characterization of rds (PMOS)
1.E+10
y = 1.31E+07x-‐9.52E-‐01
R² = 9.91E-‐01
⇒ rds ≅
1.E+09
1,31.10 7 × L(m)
I dsat ( A)
rds (Ω
Ω)
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.00E-‐03
1.00E-‐02
1.00E-‐01
1.00E+00
Idsat/L (A/m)
1.00E+01
1.00E+02
1.00E+03
7
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Characterization of λp
[
]
I ds = I dsat 1 + λ (Vds − Veff ) avec λ =
13,1× L( µm)
76mV −1
⇒ λp =
I dsat ( A)
L( µm)
rds ≅
•  Standard deviation
•  Fixed length design
(e.g. L=10µm)
è
λ p = 7,65.10−3V −1
2 Leff
k ds =
2ε 0ε r
qN a
rds modèle vs. rds mesure
1.E+10
1.E+09
rds (modèle, Ω )
± 25%
k ds
Vds − Veff + Φ 0
1.E+08
1.E+07
y = 0.5026x1.0419
R² = 0.9915
1.E+06
1.E+05
1.E+04
1.E+04
1.E+05
1.E+06
1.E+07
rds (mesure, Ω )
1.E+08
1.E+09
1.E+10
Lab #1: Technology characterization
•  BSIM3v3 models
– 
– 
– 
– 
– 
/soft/DKits/Ams/HK_410/spectre/c35/cmos53.scs
Identification of various models
Analysis of ‘modn’ and ‘modp’
Find VTH0 (V), U0 (cm2/Vs) and Tox (m)
Calculation of µ.Cox
TOX = ?
ε0 = 8.85e-12 F/m
εr = 3.9
Cox =
ε 0εr
TOX
•  Calculation of µ.Cox and rds by MOST characterization
8
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
The step-by-step method
•  All the steps below will be easier and you will reduce the risk of
error if you keep the initial circuit topography for your smallsignal model…
•  Step 1: identify your input i.e. the magnitude that will vary during
your small-signal analysis and keep-it unaltered anytime
•  Step 2: replace I and V sources by their small-signal model
•  Step 3: replace each transistors by their small-signal model
including labels for g, d, s
•  Step 4: add electrical connections as in your initial circuit
•  Step 5: identify all required vgs and eliminate related voltagecontrolled current sources when vgs=0
•  Step 6: identify your output variable, eventually rearrange your
circuit and solve the obtained circuit
9
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
Your first Analog Design
Vdd=3.3V
T8
T1
T2
V-
T3
Vbias
T9
T6
T5
Ids7
T7
V+
Ids11
T10
Vout1
T11
T16
Vout
Cf
T12
Ids13
T13
T4
Voltage Reference
10
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Homework & Lab
•  Homework
–  Design T1 to T4 for Vbias=0.6V and IT1=10µA
–  Derive a small-signal model of the circuit to
determine sensitivity to Vdd of both Vbias and IT1
–  Compute these sensitivities
•  Lab
–  Verify the biasing point using a ‘Operating Point’
simulation (both Vbias and IT1)
–  Verify the sensitivity to Vdd of the biasing point using
a ‘DC’ simulation (both Vbias and IT1)
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
11
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Your first Analog Design
Vdd=3.3V
T8
T1
T2
V-
T9
T6
T5
T3
Vbias
Ids7
T7
V+
Ids11
T10
Vout1
T11
T16
Vout
Cf
T12
Ids13
T13
T4
Voltage Reference
Current Source
Homework & Lab
•  Homework
–  Design T13 for IT13=50µA
–  Derive a small-signal model of the circuit to
determine rout
–  Compute rout
•  Lab
–  Verify the biasing point using a ‘Operating Point’
simulation (IT13)
–  Verify the output resistance using a ‘DC’ simulation
12
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Outline
•  Large- and small-signal models for MOST in
strong-inversion
–  Overview of theoretical background
–  Experiments
•  DC Small-Signal Model of a CMOS Analog
Circuit
–  Straightforward approach
•  Exercises
–  A basic Voltage source : determine Vdd dependency
–  A basic Current source : output resistance and Vdd
dependency
–  A basic amplifier : voltage gain
Your first Analog Design
Vdd=3.3V
T8
T1
T2
V-
T3
Vbias
T9
T6
T5
Ids7
T7
V+
Ids11
T10
Vout1
T11
T16
Vout
Cf
T12
Ids13
T13
T4
Voltage Reference
Current Source
Common source
voltage amplifier
13
Analog IC design - 2014/2015 - Chapter 2
19/09/2014
Homework & Lab
•  Homework
–  Derive a small-signal model of the circuit to
determine the voltage gain
–  Compute the voltage gain
–  Design T10 for a voltage gain of 500
•  Lab
–  Verify the voltage gain using a ‘DC’ simulation
–  Verify the voltage gain using a ‘AC’ simulation
Références
•  D. Johns and K. Martin, "Analog Integrated Circuit
Design", John Wiley & Sons, Inc. 1997, ISBN
0-471-14448-7
•  P. Allen and D. Holberg, "CMOS Analog Circuit Design",
2nd Edition, 2002,Oxford University Press, ISBN
0-19-511644-5
•  B. Razavi, "Design of Analog CMOS Integrated Circuits",
McGraw Hill, 2001, ISBN 0-07-238032-2
•  P. Gray, P. Hurst, S. Lewis,and R.G. Meyer, “Analysis and
Design of Analog Integrated Circuits”, 4th Edition, John
Wiley and Sons, 2001, ISBN 0-471-32168-0
14

Download Report