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URL
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Characterization of Current-Mode CMOS R-2R Ladder Digital
-to-Analog Converters
Watanabe, Kenzo; Wang, Lei; Fukatsu, Yasunori
IEEE Transactions on Instrumentation and Measurement.
50(6), p. 1781-1786
2001-12
http://hdl.handle.net/10297/3527
publisher
Rights
This document is downloaded at: 2016-02-25T12:26:03Z
IEEETRANSACTIONSONINSTRUMENTTWIONANDMEASUREMENTVOL．50，NO．6，DECEMBER2001
1781
CharaCterizationofCurrent−ModeCMOSR＿2R
LadderDigltal−tO−AnalogConverters
LeiⅥねng，ⅥsunoriFukatsu，andKenzoWatanabe，FbllowlLEEE
AbstTVCトーA digital−tO・analog（D／A）converter based on the
R−2Rladderis丘rstaTlalyzedintermsofthepowerconsumption，
topointoutthatthectlrrent・mOdeisthelowestpowerdissipation
COunterpartOfthevoItage・mOde・Theintegralnonlinearity（INL）
analysesandthecharacterizationmethodsofthecurrent．mode
I）仏converterarethenpresentedtoidenti付theerrorsources．The
methodsareappliedtoan8−biHⅣAconverterhbricateduslng
O・6FLm CMOSprocess・MeasuredresultscomparedwithINL
analysesindicatethatthedominanterrorsourceofaprototype
COnVerteristheresistanceofthemetalinterconnectbetweenthe
ladderandthebondingpad，andtheINLoftheladderitselfisl．2
LSB．
Ln血7bms−CMOSintegrated circuit，Current−mOde）dig−
ital−analogconversion，lowpower，reSistiveladder．
ThispapernrstreviewstheR−2RladderD／Aconvertertopolnt
Outthatthecurrent−Orinverse−mOdeconngurationisbestsuited
fbrlow−POWerOPeration・Then，methodstocharacterizethecur−
rent−mOdeconverterarePreSented．Perfbrmancesofan8−bitD／A
COnVerterfabricateduslngtheO・6FLmCMOSprocessarennally
PreSentedtodemonstratethecharaCterizationmethods．
II．R−2RLADDERD／ACoNVERTERS
Fig・1showsacircuitdiagramofaconventionalvoltage−mOde
R−2RladderD／Aconverter∴隼isthereftrencevoltageand
di（i＝1，2，‥・，n）isthen−bitbinarynumbertobeconverted
intotheanalogvoltage・AssumlngnOWthatallresistorsare
exactlymatchedandtheswitchesareideal，thentheimpedance
I．INTRODUCTTON
T慧 CMOSprocessiscommonlyusedfbrmixedanalog
digitalsystemintegration，because the advancein
Seenfromthenode①totherightiS字Randtherefbrencevoltage
SWitchedbydiisattenuatedby2￣ttoreachthenode①．The
OutPuttも。tOftheD／AconverteristhusglVenby
nne−line technologymakesitpossible tointegrate alarge
SyStemOntOaSmallsiliconarea・Oneoftheissuesaccompa−
叱ut＝（d12￣1＋d22￣2＋‥・＋dm2−m）×隼＝宗佑（1）
nylngSuChahigh−densltylntegrationisthepowerdissipation，
andlow−VOltage andlow−POWer designs are highly recom−
か＝d12m−1＋d22m−2＋‥・＋dm・ （2）
mendedl1］，【2］・Thisisespeciallytruefbrananalogcircuit，
andapromlSlngCandidateisacurrent−mOdecircuitthathas
the potentialcapabilities of wideband and wide dynamic
Slgnalprocesslngunderthelowsupplyvoltage・Current−mOde
analog−tO−digital（AD）anddigital−tO−analog（D／A）converters
ThecurrentflowlngthrougheachleglSglVenby
dl佐一叱tlt
71＝
（3）
2月 ，
Will，thereR）re，bekeycomponentsinmixedanaloganddigital
ASICs［3】．
′／′l二．−
Anydataconverter，AD，OrD／Aconverter，requlreSthequan−
J′＝
tizedreftrence・Astraightfbrwardwayofproducingthequan−
tizedrefbrencesistheresistorstnngortappedresistor．This
2月
（宜＝2，3，・‥，れ＋1）
（4）
architectureisexclusivelyusedfbrhigh−SPeedflashAノDcon−
VerterS，butisseldomappliedtoaD／Aconverterbecausethe
Wheredn＋1＝0．
SWitchtreetomultiplexthequantizedreftrencesdependingon
Ifdi＝1，thecurrentIiissuppliedbythereftrencesource．
adigitalinputtakesalongtimetosettlel4］，［5］．Anothersimple
Ifdi＝0，0ntheotherhand，IiSinkstotheground・Sinceno
arChitectureistheR−2Rladder・Itoperatesasahigh−SPeedcur−
Currentflowsoutoftheterminal①，thetotalsourcecurrentis
rentdividerl6］，andthesmalldevicecountisquiteattractive
equaltothetotalsinkcurrent
toanASICinwhichalargenumberofD／Aconvertersarere−
quiredl7］，［8］．ThemainerrorsourcesoftheR−2RladderD／A
∑鵜＝−∑扁沃一左石 （5）
COnVerteraremismatchesoftheswitchon−reSistances，butthe
advancesinCMOS伽e−linetechnologyhavegreatlyimproved
thematchingaccurac）Ofswitches・Basedonthesetechnolog−
icalaspects，theR−2Rladderisrevisited．
andthepowersuppliedbythereftrencesourceisalldissipated
intheladder・Thepowerdissipationisthus
P＝∑帖佐・ （6）
ManuscnptreceivedDecember13，2000；revisedSeptember30，2001．
TheauthorsareWiththeResearChInstituteofElectronics，ShizuokaUniver＿
Slty，Hamamatsu，Japan．
PublisherItemIdentinerS0018−9456（Ol）10978−2．
Fig・2plotsthepowerdissIPationofthe4−bitD／Aconverteras
afunctionoftheinputcode・ExceptfbratrivialcasewhenD＝
0018−9456／01＄10．00◎2001IEEE
1782
IEEETRANSACTIONSONINSTRUMENTATIONANDMEASUREMENT，VOL・50，NO・6，DECEMBER2001
Fig．4．D／Aconverterunderresistancemeasurement．
Fig．1．Ⅵ）ltage−mOdeR−2RladderD／Aconverter．
WhereRriistheresistancelookingtowardtheright−handend
5 2 5 1 5 0
2 1 0
％川
Oftheladder．Thecurrentflowlngthrougheachlegisthenex−
PreSSedasfollows
壷一1
ん
圭＝芸（1−ど宣）n（1＋どた），（戌＝1，2，…，可・（10）
0 1 2 3 4 5 6 7 8 9 101112131415
Introducingtheweightingfactor
DigitalinputD（decimalnotation）
W1＝拍一己1）
Fig．2．Normalizedpowerdissipationofa4−bitR−2RladderD／Aconverteras
i−1
afunctionofthedigitalinput．
1′
Wi＝妄（1−El）H（1＋どた）
WeCanreWrite（11）inthematrixfbm
VG：VertualGround
dn
70
Ⅰ。ut（VG）
L
r
i。ut（VG）
L
r
0 0 ・ ・ l
盟
In．
1
0 0 ・ ・ 0
1
R p（
n
0 1 ・ ・ 0
Ⅰ
。
1 0 ・ ・ 0
R叩
ん． （13）
The matrix representation（13）indicates that the weighting
factor，and thereby the mismatch Ei，Can be determined by
Fig．3．Current−mOdeR−2RladderD／Aconverter．
SettlngOnlydi＝1andmeasunngI。。t．
0，theplotsare．symmetricalarOundD／2n＝0・5，Wherethe
Thecurrentmeasurementdescribedaboveprovidesndata
fbrtheresistanceratio．Ann−bitR−2RladderD／Aconverterin−
dissIPationismlnlmum．ThisholdstrueOfanyR−2RladderD／A
Cludes2nresistors．Tbknoweachresistancevalue，nadditional
COnVerter．ThecurrentflOwlngthrougheachlegattheminimum
dataarerequired・Suchdatacanbeobtainedbyapplyingacon−
POWerdissipationisglVenby
StantCurrentIintOtheI。。tteminalandmeasunngthevoltage
atthereftrenceterminal，aSShowninFig．4．Thevoltagetl
WhenonlydlissettolandtheotherbitsareSettOOisglVenby
l：・
（7）
ム＝元
坑＝凡11Jin． （14）
ム＝一占ム（ま＝2，3，・‥，叫1）・（8）
Eq．（8）indicatesthatifZlisreplacedbythereftrencecurrent，
thesamearChitectureresultsinthecurrent−mOdeD／Aconverter
ShowninFig．3．Thisconngurationisthusinterpretedasthe
lowestpowerdissipationcounterpartoftheR−2RladderD／A
COnVerterS．
The current−mOde R−2RladderD／A convertercanbe char−
From11andEl，WeCanknowRplandR，1・Next，thevoltage
VBwhenonlyd2issettolisglVenby
ヰ＋監言語監日記月品（15）
SinceR，1glVenby
acterizedbythefbllowingproceduresl9］，［10】．LetEibethe
み1＝凡1鴫21デ （16）
resistancemismatchatthenode①
isalreadyknown，WeCanObtainRslandRp2by（15）and（16）・
月pi一月γ壱
どi＝
月p豆＋月ri
（9）
Repeatlngthisprocessntimes，OneCanmeaSurealltheresis−
tancevalues．
WANGetal．：CHARACTERIZATIONOFCURRENT−MODECMOSR−2RLADDERDIGITAL−TO−ANALOGCONVERTERS
n（1＋どた）＝1＋∑どた
（17）
L，。t＝Iid。al＋△I
＝∑2￣id詰＋△J
■ヽ
■
仰「￣
＿
＿
「〆 ．
．
W 50 100
l ■
∩
■
3
20町
長
150 2 4 6
0 0 0
WeCanObtaintheoutputcurrent
6 4 2
0 0 0
Approximatlng
︵斡SJ︶合で空白弓〇三d払む召H
Once the resistance mismatchesareknown，theintegral
nonlinearity（INL）ofthe convertercanbeeasily estimated．
1783
＿
＿
了
W
（18）
壱＝1
andisglVenby
筈＝一号（d1− 差2一（叫dた）
22
（d2−墓2−…斗‥・一打19）
5 0
0．
g2
︵西SJ︶合でd呂叫召昌扇払3月
where△Iis the errorcurrent due to the resistance mismatch
The丘rst−Orderrepresentation（19）oftheerrorcurrentindicates
thatINLassumeslocalmaximaatminorcamiesandmaximum
2−（n＋1）Ir・Therefbre，E＜2−nisrequiredfbrn−bitresolution・
The other error sourcesare On−reSistances of switches and
Wireresistancesfromtheladdertotheoutputterminals．The
INLsduetotheseerrorsourcesarealsoshowninFig．5，Where
an8−bitD／AconverterwiththenominalresistanceR＝Rs＝
Rp／2＝2030andtheresistan？emismatchofO・4％isassumed・
0 0 0 0
3 2 1
to LSB，the maximum error current should be smaller than
︵再∽d合でd呂弓呂l邑首ヨ
atthem亘iorcarry，aSShowninFig．5（a）・Themaximumerror
currentis2−1EIZr．FortheD／Aconversiontobeaccuratedown
． ．l l
l■
−
半丁
−
■
’． ＼
‥
仁
l ▲．
−
＿
l
50
1 0 0 150
3
’
▼
r ▼
’
Fig．5（a）showsINLduetoresIStanCemismatch．Thepromeis
asymmetricalwithrespecttothemqorcarry．TheINLpronle
Whenthemismatchofon−reSistanceispresentinadditiontothe
resistancemismatchisshowninFig．5（b）．Theon−reSistances
Ron，dOfthoseswitcheswhicharedrivenbythedigitalinput
≠
（C）
Fig．5．INLpronlesduetomismatchesin（a）resistance，（b）on−reSistanceof
SWitch，and（C）wireresistance．
diareaSSumedtobellnwhilethoseRon，百drivenbydiare
Cenl Cem2
assumedtobeO．Itcanbe seenthatINLduetoon−reSistances
issymmetricalwithrespecttothemqOrCarryandassumesthe
COnCaVe−uPPrOfile・IfRon，d＜Ron，百，thenINLassumesthe
COnCaVe−downpro丘Ie．Fig．5（C）showstheefftctofthewirere−
Sistance．ThewireresistanceR。utfromtheladdertoI。utter−
minalisassumedtobe300，WhilethatofR元首tOZolltterminal
isassumedtobeO．Theresistanceofthewireinterconnectloses
エ
M⊥
3
壷 ⅥM 2
￣
￣
謂
○
Ⅰ
。
ut
Ml
Ⅰ
。
u
t
0
thesymmetryinFig．5（a）and（b），andshiftsthemaximum’INL
towardLSBifRout＞R757I盲andviceversa・Thesepropertiesof
INLpronlescanbeusedtoidentifytheerrorsources．
Cbck Cご
ldl
d2也
d3d3 ￣
￣d7d7 d8b Reght
er
ⅠⅠⅠ．CMOSLADDERD／ACoNVERTER
I t l The characterization methods ofthe R−2RladderD／Acon−
l l
dt も d3 d7 血
d蜘血hput
Verterdescribedintheprevioussectionhavebeenappliedtoan
8−bitD／AconverterfabricateduslngtheO．6IJmCMOSprocess・
ThecircuitdiagramoftheD／AconverterisshowninFig．6．The
resistorRinFig．3isreplacedbytheunitnMOStransistoroper−
Fig・6・Circuitdiagramofan8−bitD／AconverterfabricatedbyO・6ItmCMOS
atlnglnthelinearreg10n，andthefburunittransistorsfbrmthe
thedigitalinputdianddiOPeratealsoasswitches・Therefer−
unitce11fbrl−bitconversion．Thoseunittransistorsdrivenby
encecurrentwasassumedtobe256pA．
1784
IEEETRANSACTIONSONINSTRUMENTATIONANDMEASUREMENT，VOL・50，NO・6・DECEMBER2001
25
ノ
20
／
／
ノ了
S15
∈
ヽ J
主10
5
0
／
。
i。
＝
2。
2．
… ）
0 20 40 60 80 100 120
tr（lA）
Fig．8．CurrentversusvoltagecharacteriSticsatthereferencenode．
Fig．7．Microphotographoftheprototypechip．
Wheretheusualnotationsareusedfbrtransistorparameters・The
22
0
500
克＝〃晶（筈）（侮一佐一等）侮，
︵望む呂召莞巴ぢdj
ThedraincurrentIDOfannMOStransistoroperatlnginthe
linearreg10nisglVenby
／
3
2．
4
1．
2
linearoperationislimitedto
tbS≦l七5−1㌢．
（21）
0．5 1 1．5 2 2．5 3 3．5
ChannellengthofthenMOStransistor（pm）
Themaximumdraincurrentisthus
（t七g一作）2
Jpmax＝〃mG諾
（22）
Fig．9．TheequlValentresistanceversusthegatelengthofannMOStransistor．
300
TheunittransistorsintheMSBcellcarrythecurrentZr／2＝
250
128PAandthiscurrentshouldbesmallerthanIDmax．This
200
COnditionspeciBestheaspectratioasfbllows：
Inderiving（23），theprocessparametersFJnC。X＝40IJAⅣ2，
1与＝0・8Vandthebiasvoltagelち＝2・5Vareassumed・
A muchlarger aspect ratio than that speci丘edby（23）is
PreferabletolowertheequlValentresistance，therebythepower
dissipation，andalsotoreducetheharmOnicdistortionwhenthe
D／Aconverterisappliedtoanattenuatorandamultiplier・With
thislowpowerandlowdistortioninmind，threeaspectratios
W几＝200FLm／3．FLm，200ILm／2．4pm，and200〃′m／1．2pm
苛きちdち○
（筈）≧2・2・ （23）
150
100
50
0
−50
−100
−150
−200
−250
−300
DigitalinputD（decimalnotation）
areChosenfbrprototypechips．
Fig．7showsamicrophotographoftheprototypechipwith
（W几）＝200FLm／3FLm．Inthecentralpart33unittransistors
Fig・10・ThnsfercharaCteristicsoftheprototypeD／Aconverter：W几＝200
〃m／3〃m．
arrangedintwocolumnscanbeseenfbrmlngtheladderstage．
Itcanalsobeseenthattheunittransistorisfbrmedbythepar−
（L＝−256FLA）reftrencesareSymmetrical，Whichprovesthat
allelconnectionof4transistorswithW几＝50FLm／3〃m．The
theladderD／Aconverterisavailablealsofbranattenuatorand
rightmostpartisthereglStertOStOrethedigitalinput．
amultiplier．Fig．1lshowstheINLobtainedfromthemeasured
Fig・8showsthecurrentversusvoltagecharacteristicsatthe
reftrencenode．Thisresultindicatesthattheunittransistoroper−
atesasalinearresistorof23200Verthewidereftrencecurrent
transftr charaCteristics．Companng the profiles with those
ShowninFig．5，itcanbefbundthatthedominanterrorsource
isthewireresistance．Thebest一員tsimulationuslngSpicehas
range．Fig．9showstheequivalentresistanceasafunctionof
estimatedthatthewireresistancesfromtheladdertotheI。ut
thegatelength．Thelinearrelationcon丘rmSthattheaspectratio
Fig．10shows the measured transftr characteristics．The
andI。。tPadsare8．80and12．80，reSPeCtively．Thesevalues
arequltereaSOnableinviewofthe丘ne−lineCMOSprocess．
PerfbrmancesoftheCMOSladderitselfareevaluatedbyex−
transftrcharacteristicsfbrthesource（I，＝256pA）andsink
Cludingtheeffbctofthewireresistances・ThbleIlistsequivalent
linearlyscalestheequivalentresistance．
WGetal・‥CHARACTERIZATIONOFCURRENT−MODECMOSR−2RLADDERDIGITAL−TO−ANALOGCONVERTERS
1785
4 2 0 8 6 4 2 0 2 4 6
︵閂SJ︶卓雇呂弓喜一空訝盲Ⅰ
PrOfi1ewiththatshowninFig．5（b），itisclearthatthemismatch
inswitchon−reSistancealsodegradesINLtol．2LSB．
IV．CoNCLUSION
CurrentandvoltagemeasurementstocharaCterizetheR−2R
0
150 200 250
ladderandtheINLpronlestoidentifytheerrorsourcesofthe
ladder−basedD／Aconverterweredescribed・Thesetechniques
︵斡Sd丘で望月召0日︻d払む盲i
WereapPliedtothe8−bitCMOSladderD／Aconverterfabri＿
4 2 0 8 6 4 2 0 2 4 6
CateduslngtheO・6pmCMOSprocess・Themeasuredresults
haveindicatedthatthedominanterrorsourceoftheprototype
COnVerteristhewireresistancefromtheCMOSladderstageto
thepondingpad，andtheINLoftheCMOSladderisl．2LSB．
Theprototypeconverterwasfabricatedbyfullydigital−COm−
Patibleprocess・Thecircuitconfigurationissimple，andthe
0
50 100 150 200 250
（b）
Fig・11・IntegralnonlinearityoftheprototypeD／Aconverter：（a）Ir
256IJA；（b）Z，＝−256IJA．W／L＝200FJm／3FLm．
device countis small・The analog bandwidth extends up
tolOO MHz，and the totalharmOnic distortionisless than
O・1％・Owingtothesedistinctftatures，theCMOSladderD／A
COnVerterdescribedhereinisqulteuSefulfbrhigh−SPeedD／A
COnVerSionandvideoslgnalprocesslnglnamixedanalogand
digitalASIC・ImprovlngINLbylowenngthewireresistances
isafuturework．
5
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［10］B・V訂ghaandI・Zaltan，“Calibrationalgorithmforcurrent−OutPutR−2R
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753−758．
resistancesandmismatchesinthe丘rstfburMSBcellsevalu＿
atedbythecurrentandvoltagemeasurementsdescribedinthe
PreVioussection・Rpincludestheresistanceoftheswitchtran−
Sistor・Thedeviationoftheequivalentresistancefromthenom−
inalvalue，andthemismatchincreasewiththelattercell．This
isduetotheaccumulateduncertaintylnthewireresistances．
TheO・4％resistancemismatchinthefirstcell，Whichdominates
INLoftheCMOSladder，SuggeStSthatINLbelLSB・Fig・12
ShowsthepracticalINLoftheCMOSladder・Companngthe
Lei Wang was bomin Shanghai，China，On
November14，1970・HereceivedtheM・S・degree
in1997andthePh・D・degreeinenglneenngfrom
theUniversltyOfShizuoka，Hamamatsu，Japan，in
2001，Onthesu叫ectofR−2Rladderdigital−tO−analog
HeiscurrentlywiththeMeiyoElectricCo．，Ltd．，
Shizuoka，Japan．
1786
IEEETRANSACTIONSONINSTRUMENTATIONANDMEASUREMENT，VOL．50，NO．6，DECEMBER2001
YasunoriFukatsu was borninIzumo，Japan，
in1978・He received the B・E．degreein system
englneenngfromShizuokaUniverslty，Hamamatsq，
Japan，in2001・HeiscurrentlypursulngtheM・E・de−
greeintheGraduateSchoolofShizuokaUniversIty・
Hiscurrentresearchinterestsareinthecircuitde−
KenzoWatanabe（M’74−SM’86−F’93）receivedthe
B・E・andM・E・degreesinenglneeringfromShizuoka
University，Hamamatsu，Japan，in1962and1966，re−
SPeCtively，andtheDr・Eng・degreefromKyotoUni−
VerSity，Kyoto，Japan，in1976．
HeisaProfessorattheResearchInstituteofElec＿
Slgnandmeasurementofthedigita1−tO−analogcon−
tronics，Shizuoka，Universlty・・HewasattheUniver−
Verter．
SltyOfCalifomia，LosAngeles，aSaVisitingPro一
hssor丘・Om1982to1983．
Dr．Watanabe received the Andrew R．ChiBest
PaperAwardandtheI＆MSocietyAwardfromIEEE
IMSocietyin1984and1999，reSPeCtively，andtheSaitoAwardfromtheChion
Institutein1990andtheThkayanagiMemorialAwardin1994．Hehasalso
beendesignatedanEmeritusProftssorofXidianUniverslty，Xi，an，China，in
1997．HeisanAsSociateEditorofIEEETRANSACTIONSONINSTRUMENmrION
ANDMEASUREMENT．

Class A CMOS Current Conveyors

A High-Resolution, Linear Resistance-to