088768 - architetture avanzate dei calcolatori

088768 - ARCHITETTURE AVANZATE DEI CALCOLATORI
AA 2013/2014
http://home.deib.polimi.it/silvano/aac.htm
Prof. Cristina Silvano
email: [email protected]
Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB)
Politecnico di Milano
Goals of the AAC course
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Provide an overview of the most recent and advanced
computer architectures
Introduce the basic micro-architectural mechanisms
found in modern microprocessor architectures
Provide the reasoning behind the adoption of advanced
computer architectures
Cristina Silvano – Politecnico di Milano
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Advanced Computer Architectures:
IBM Blue Gene P Supercomputer
Cristina Silvano – Politecnico di Milano
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Advanced Computer Architectures:
Smart phones
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Advanced Computer Architectures:
Intel® Core™ i7-3770T Processor
(Nehalem, up to 3.70 GHz)
160mm² die @ 22nm
1.40 billion transistors.
Cristina Silvano – Politecnico di Milano
# of Cores
4
# of Threads
8
Clock Speed
2.5 GHz
Max Turbo Frequency
3.7 GHz
Intel® Smart Cache
8 MB
Instruction Set
64-bit
Instruction Set Extensions
SSE4.1/4.2, AVX
Embedded Options Available
No
Lithography
22 nm
Max TDP
45 W
Recomm. Customer Price
TRAY: $294.00
Max Memory Size
32 GB
Memory Types
DDR3-1333/1600
# of Memory Channels
2
Max Memory Bandwidth
25.6 GB/s
ARM Cortex-A8 core processor
in Apple A4 System-on-Chip
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Based on the ARMv7 architecture
It’s a dual-issue in-order execution design
The Apple A4 at 1 GHz (45nm manufactured by Samsung from March
2010 to present), a System-on-Chip that combines an ARM Cortex-A8
and a PowerVR GPU, is in the:
• Original iPad, April 2010
• iPhone4: June 2010 (Black; GSM), February 2011 (Black; CDMA),
April 2011 (White; GSM & CDMA)
• iPod Touch (4th generation): September 2010 (Black model),
October 2011 (White model)
• Apple TV (2nd generation): Sept. 2010
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ARM Cortex-A9 MP core processor in
Apple A5 System-on-Chip
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Based on the ARMv7 architecture
It’s a dual-issue in-order execution design
The Apple A5 at 1 GHz (45nm to 32 nm manufactured by Samsung
from March 2011 to present), a System-on-Chip that combines a dual
core ARM Cortex-A9 with NEON SIMD accelerator and a dual core
PowerVR GPU, is in the:
• iPad 2 (A5 dual-core 45 nm) – March 2011; (A5 dual-core 32 nm) –
March 2012
• iPhone 4S (A5 dual-core 45 nm) – October 2011
• Apple TV 3rd generation (A5 single-core, 32 nm) – March 2012
• iPod Touch 5th generation (A5 dual-core 32 nm) – October 2012
• iPad Mini (A5 dual-core 32 nm) – November 2012
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Apple A6 System-on-Chip
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Apple A6 SoC was introduced on Sept. 2012 for the iPhone 5
Apple states that it is up to twice as fast and has up to twice the
graphics power compared to its predecessor the Apple A5
The A6 uses a 1.3 GHz custom Apple-designed ARMv7 based dual-core
CPU, called Swift, and an integrated triple-core PowerVR SGX 543MP3
GPU.
The A6 chip for iPhone 5 incorporates 1GB of LPDDR2-1066 RAM and
provides double the memory capacity of iPhone4S while increasing the
theoretical memory bandwidth from 6.4 GB/s to 8.5 GB/s.
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Apple A6 System-on-Chip
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ARMv7s ISA dual core
Triple-core PowerVR
SGX 543MP3 GPU
1MB L2 cache
1.3 GHz
32nm Samsung
96.71mm2 (22% smaller
than A5)
Cristina Silvano – Politecnico di Milano
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Moore’s Law (1965) says that the numbers of
transistors on a processor will double every
18 to 24 months
Cristina Silvano – Politecnico di Milano
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Stopper: Max. Clock Freq. Wall
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Chip density is
continuing increase
~2x every 2 years
Clock speed is not
Expose parallelism in a
coarser level than ILP
Source: Intel, Microsoft (Sutter) and
Stanford (Olukotun, Hammond)
Cristina Silvano – Politecnico di Milano
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Stopper: On-Chip Temperature Wall
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Paradigm shift : Multi-core architectures
ARM 9
180 nm
11.8 mm2
130 nm, 5.2 mm2
90 nm, 2.6 mm2
65 nm
1.4 mm2
Source: STMicroelectronics
Intel 80 core
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NVIDIA Fermi GPU
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NVIDIA Tesla GPU
Kepler GK110 Architecture
• 7.1B Transistors
• 15 SMX units (2880 cores)
• >1TFLOP FP64
• 1.5MB L2 Cache
• 384-bit GDDR5
• PCI Express Gen3
Cristina Silvano – Politecnico di Milano
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Dark Silicon Problem
DARK SILICON : chip fraction not
usable due to the power budget
Processor frequency is affected by
technology effects (e.g. Vth)
AAC Course Schedule
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Schedule: First Semester 2013-2014 (FALL 2013)
WEDNESDAY 10.15 - 12.15
Location: L.26.11 Leonardo Campus
THURSDAY 10.15 - 12.15
Location: L.26.16 Leonardo Campus
Cristina Silvano – Politecnico di Milano
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Contact Information
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Office hours for students:
Tuesday 10.00 - 11.00 at DEIB, Via Ponzio 34/5 First floor –
Internal phone number: 3692 (better to send an email to get
an appointment).
Main Contact:
The students can contact prof. Cristina Silvano by
e-mail ([email protected])
by indicating: Subject: AAC COURSE Milano,
Your_Surname, Your_Name, Your_POLIMI_ID_NUMBER
Please use your POLIMI student e-mail account:
[email protected]
Cristina Silvano – Politecnico di Milano
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AAC Teaching Assistants
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Prof. Giovanni Agosta
e-mail ([email protected])
Prof. Gerardo Pelosi
e-mail ([email protected])
Cristina Silvano – Politecnico di Milano
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AAC Course Info
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Teaching Activity: The course consists of 5 CFU and it is
organized in 30 hours of lectures and 20 hours of
written/tool-based exercises to prove the concepts
presented during the lectures.
Pre-requirements: Basic concepts on logic design and
computer architectures.
Cristina Silvano – Politecnico di Milano
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AAC Final Exam
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FINAL EXAM:
The final exam consists of a written exam. For each
written exam, a max. score of 33 points will be
assigned: max. 15 points will be assigned for the
solution of the exercise part and max. 18 points will be
assigned for answering to the theory part.
It is possible to ask an OPTIONAL project to the
instructor. The project must be concluded by January
31st, 2014 (firm deadline). The project assign an
additional score up to max 5 points. The additional
points given by the project will be added to the score of
the written exam only if the final score of the written
exam will be sufficient (>=18).
Cristina Silvano – Politecnico di Milano
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AAC Teaching Material
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Additional information in slides and papers available
through the course webpage:
http://home.dei.polimi.it/silvano/AAC.htm
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If you're using MOZILLA FIREFOX AS WEB BROWSER, for a correct
visualisation and printing of the PDF SLIDES, please use the SAVE AS
option and save the PDF FILE on your laptop for correct
visualisation and printing.
Reference Book: "Computer Architecture, A Quantitative
Approach", John Hennessy, David Patterson, Morgan
Kaufmann, Fourth Edition.
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Support for the international students
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AAC course is offered in Italian
Teaching materials (slides/papers/textbook) available in
English
Final exam can be done in English
Teaching support available in English
Please notice international students can follow the
course HPPS (High Perfomance Processors and System)
held by prof. Donatella Sciuto during the Second
Semester 2013 - 2014. HPPS Course is completely offered
in English. AAC course objective and program are aligned
with HPPS course.
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March 2013
Overview of the AAC topics
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How to increase performance while decrease the design cost ?
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Can we gain more ?
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RISC: Reduced Instruction Set Computer
Pipeline
Branch prediction
Instruction Level Parallelism (ILP)
Multithreading
Multiprocessors
Still performance does not scale ?
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Memory hierarchy
Cache organization
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Main lectures topics (1)
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Review of basic computer architecture definitions and components
(Central Processing Unit, Memory System, Input/Output Interfaces,
Communication System)
Basic performance evaluation metrics of computer architectures
Memory hierarchy: Basic and advanced concepts. Multi-level caches.
Performance evaluation, optimisation techniques.
Central Processing Unit: the RISC approach (Reduced Instruction Set
Computer).
Cristina Silvano – Politecnico di Milano
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Main lectures topics (2)
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Techniques for performance optimization:
• Pipelining: The problem of hazards: structural, control and data
hazards; Optimization techniques to solve the problem of
hazards
• Branch prediction techniques: Static and dynamic branch
prediction techniques
• Speculative execution
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Sequential vs. Pipelining Instruction Execution
I1
IF
ID
EX
I2
MEM
WB
IF
10 ns
Cristina Silvano – Politecnico di Milano
ID
EX
10 ns
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MEM
WB
…
Main lectures topics (3)
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Instruction Level Parallelism (ILP):
• Static and dynamic scheduling;
• Superscalar architectures;
• VLIW (Very Long Instruction Word) architectures;
Cristina Silvano – Politecnico di Milano
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Instruction Level Parallelism:
Example of 2-issue processor
I1 I
1
I2 I
2
I3
I4
I5
I6
I7
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
2 ns
IF
ID
EX
MEM
IF
Time
WB
Instruction Per Clock = 2
CPI = Clock Per Instruction = 0.5
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
2 ns
2 ns
I8
I9
2 ns
I10
Cristina Silvano – Politecnico di Milano
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Beyond ILP: Multithreading
Threads: Independent sequences of instructions
…
Single-threaded program
Multi-threaded program
Main lectures topics (4)
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Beyond ILP:
• Multithreading (Thread Level Parallelism – TLP)
• Multiprocessors and multicore systems: taxonomy,
topologies, communication management, memory
management, cache coherency protocols, example of
architectures
• System-on-Chip and Network-on-Chip architectures;
Digital Signal Processors; Stream processors and
vector processors; Graphic Processors
Cristina Silvano – Politecnico di Milano
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