// file sink.cpp #include "sink.h" void sink::sink_proc() { while(true) { printf("\033[01;31m[SINK] reads %d @ simulation time %d\n\033[0;39m",input-­‐>read(), (int)sc_simulation_time() ); } } // file source.cpp #include "source.h" void source::src_proc() { wait(5, SC_NS); // get off of time = 0 for (int i = 1; i < 13; i++) { output-­‐>write(i); printf("\033[01;34m[SOURCE] writes %d @ simulation time %d\n\033[0;39m",i, (int)sc_simulation_time() ); } } // file hw_fifo.cpp #include "hw_fifo.h" void hw_fifo::r_proc() { // read while(true) { wait(); cout << "[HW_FIFO] data_out_was_read before wait " << data_out_was_read << " e_count " << e_cnt << " @ simulation time " << sc_simulation_time() << endl; wait(0,SC_NS); // so can read every clk // cout << "[HW_FIFO] data_out_was_read after wait " << data_out_was_read << " e_count " << e_cnt << " @ simulation time " << sc_simulation_time() << endl; if(data_out_was_read && e_cnt !=0 ) { // was data read? tail++; // increment tail ptr //tail è il prossimo da leggere if(tail == DEPTH) tail = 0; // wrap the pointer e_cnt-­‐-­‐; // decrement element count } if (e_cnt == 0) // empty? data_out_valid = false; // yes, no data avail else { data_out = fifo_mem[tail]; // put data out data_out_valid = true; // data is avail } cout << "[HW_FIFO] data_out " << data_out << " @ simulation time " << sc_simulation_time() << endl; cout << "[HW_FIFO] data_out_valid " << data_out_valid << " @ simulation time " << sc_simulation_time() << endl << endl; } } void hw_fifo::w_proc() { // write while(true) { wait(); cout << "[HW_FIFO] data_in " << data_in << " @ simulation time " << sc_simulation_time() << endl; cout << "[HW_FIFO] data_in_valid " << data_in_valid << " @ simulation time " << sc_simulation_time() << endl; if (data_in_valid && e_cnt != DEPTH) { fifo_mem[head++] = data_in; // write data in fifo if(head == DEPTH) head = 0; // wrap the pointer e_cnt++; // increment element count } if (e_cnt == DEPTH) // full? data_in_ready = false; // yes, can't write else data_in_ready = true; //no, can accept more cout << "[HW_FIFO] data_in_ready " << data_in_ready << " @ simulation time " << sc_simulation_time() << endl; } } 

Chapter 3

PSoC 1 VGA PRESENTATION