VGA on a PSoC-1 Mark Bowers and Michael Lohrer ECE571 - Mixed-signal Embedded Systems Video Graphics Array display standard sync pulses 0 - 5 volts vertical sync one frame per 16.7ms (60Hz) (480 lines per frame) horizontal sync one line per 32µs (31.25kHz) (640 pixels per line) color red green blue } analog 0.0 - 0.7 volts 25.175MHz pixel clock VGA timing pixels Schematic P1[4] external oscillator P0[6] horizontal sync PSoC-1 P0[7] vertical sync P0[0] P0[1] P0[2] 75Ω÷(75Ω+R) = 5 volt ÷ 0.7 volt R = 460 Ω R G B 75-ohm terminated gnd PSoC limitations • 24MHz maximum frequency • Overclocked with external 25.175MHz oscillator • 2048-bytes RAM • We targeted 64x48x3 resolution 9216-bits/8 = 1152-bytes of VRAM RAM scheme page 0 main RAM page 1 page 2 page 3 page 4 video RAM page 5 page 6 page 7 stack • 2048-bytes total • 8-bit addressing • Eight pages of 256-bytes VRAM scheme • 64-pixels (bits) per line → 8-bytes per line • 256 ÷ 8 = 32 lines per page page 1 page 4 page 2 page 5 page 3 page 6 lines 0 ➟ 31 lines 32 ➟ 47 (256 bytes used) (128 bytes used) Paging registers STK_PP used for PUSH and POP MVR_PP used for MVI reads MVW_PP used for MVI writes IDX_PP used for indexed instructions CUR_PP used for everything else Paging modes Mode bits Page registers F[7:6] Current Page Indexed Page STK_PP MVR_PP MVW_PP IDX_PP CUR_PP 00 0 0 01 0 STK_PP 10 CUR_PP IDX_PP 11 CUR_PP STK_PP (PUSH, POP and MVI ignore these bits) Paging example or F, 0b10000000 mov X, [_VGA_ptr] ... set paging mode to 10 immediate ➟ uses page 0 indexed ➟ uses IDX_PP mov reg[IDX_PP], 1 mov A, [X+@VB_OFFSET] mov reg[SPIM_R_TX_BUFFER_REG], A mov reg[IDX_PP], 2 mov A, [X+@VB_OFFSET] mov reg[SPIM_G_TX_BUFFER_REG], A mov reg[IDX_PP], 3 mov A, [X+@VB_OFFSET] mov reg[SPIM_B_TX_BUFFER_REG], A SPI macro Addressing X location: 0 to 63 Y location: 0 to 47 (0,0) (63,0) (0,47) (63,47) Y5 ➟ High/low page Y4 Y3 Y2 Y1 Y0 X5 X4 X3 ➟ RAM address X2 X1 X0 ➟ Bit position bit mask 0: 10000000 1: 01000000 2: 00100000 3: 00010000 4: 00001000 5: 00000100 6: 00000010 7: 00000001 Display routines pixel_set( X,Y, color ) sets an individual pixel to a given color block_set( X,Y, R_block, G_block, B_block ) sets a block of 8-pixels to a given color write_line( Y, color ) fill a line with a given color write_char( X,Y, letter, color, back_color ) write a character to the screen Digital blocks • 15/16 blocks used! • Two 16-bit PWM (HSYNC & VSYNC) • Two 16-bit PWMDB (VIDON_H & VIDON_V) • Three SPIM (R, G & B) • One 8-bit Counter (Pixel clock) VGA signal generator 25.175MHz pixel clock enable COUNTER8 (Divide by 5) clock ÷ 5 (to broadcast bus) compare PWM16 (HSYNC) PWM16 (VSYNC) PWM16_DB (VIDON_H) PWM16_DB (VIDON_V) P0[6] HSYNC terminal compare P0[7] VSYNC video on VGA signal generator (continued) clock ÷ 5 (from broadcast bus) SPIM (Red pixel) P0[0] RED SPIM (Green pixel) P0[1] GREEN SPIM (Blue pixel) P0[2] BLUE vidon VGA signal timing SP HSYNC BP 96 px 48 px SP BP active FP 640 px 16 px active FP VIDON_H VSYNC VIDON_V 2 lines 33 lines 480 lines 10 lines Horizontal ISR (simplified!) region? active preserve A, X and IDX_PP inactive load X with VGA ptr set page mode to 10 dec BP counter else zero set VGA active feed SPI blocks (8 macro calls) decrement repeat counter else exit interrupt zero increment VGA ptr and line count else line = 48 set VGA inactive Resource usage SRAM Digital blocks CPU time 896 1,152 1 15 896-bytes free 1 free block! 1.1 16.7 6.6% free time! Demo!
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