10/10/14 ET1205 D2 - 02 - process 1 - Circuits and Systems

10/10/14
Project Overview
EE2C11
Course lab 2
n  You will learn how to make a design with a group.
n  Similar to1st year projects, but focus is more on structural
hierarchical design and on working within a group.
n  Each group designs a Sea-Of-Gates chip.
n  The chip is fabricated during the second semester.
n  At the end of the study year you will test the chip.
EE2L11 Project
“Ontwerp een Chip”
(Sneak preview)
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Learning Goals
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Schedule
n  EE2C11 – EE2L11
Course labs and project manual
n Version Sept 2014
n PDF on BB (EE2L11) or from Microweb TU Delft.
n  Course material from EE2C11 - Integrated Circuits.
n  Literature on Digital Systems and VHDL
n  (On-line) manuals for the different software tools.
n  Roel Grit, Projectmanagement, Noordhoff
Uitgevers B.V., 2011.
n  Information on Blackboard!
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n  2 mornings per week (8:45 – 12.30)
(Monday + Thursday) or (Tuesday and Friday)
n  Drebbelweg: rooms 1.140, 1.130, 1.060 and 0.210
n  PCs running design software under Linux:
n ModelSim
n Synopsys synthesis software
n Altera (Quartus) FPGA software
n Ocean/Nelsis layout software
n GoWithTheFlow interface
Materials
TUD/EE EE2C11 14/15 - © NvdM
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Time, Location, Infrastructure
n  Make a design using global product specifications,
including boundary conditions
n  Design in a systematic, hierarchical way
n  Use analysis together with synthesis during the design
process
n  Analyze a design at different levels of abstraction
n  Use different types of models during the design
n  Take testability into account
n  Perform the above design process within a group
n  Make a design as a part of a group design
n  Use modern computer tools during the design
n  Document the design
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GS Course Lab 2
n  Become familiar with software
n  Work in teams of 2
Q2 - Project
n  Project plan
n  System specification
n  Intermediate presentation
n  System design
n  Implementation
n  Final presentation + defense
Q4
n  Test the chip
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Schedule
Sea-of-Gates Technology
Every meeting during group design should have:
n  Chairman (prepares the agenda)
n  Secretary (creates the minutes - also sends them
to the assistant and the tutor !)
vss rail
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n-transistors
•  1.6 µm CMOS (Philips)
•  2 custom metal layers
•  per group 0.5 cm2 chip area:
50,000 NMOS + 50,000 PMOS, 32 pins
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24
23
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area
of 1
group
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vdd rail
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2
1
vss rail
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Ontwerp
specificatie
vdd
E.g. no210
NOR 2 inputs
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2
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OP Design Flow
Sea-of-Gates Cell Library
n  Cell library contains
inverter, nors, nands,
multiplexors, flipflops, etc.
n  Synthesis software
maps VHDL behavior
to VHDL structural
with cells.
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8
0
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p-transistors
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11
10
9
23.2
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n-transistors
Example morning session:
n  Initial group meeting
n  Working individually or in small groups
n  Intermediate group meeting
n  Working individually or in small groups
n  Final group meeting
p-transistors
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Interpretatie
VHDL gedrag
beschrijving
VHDL simulatie
Synthese
vdd
VHDL struktuur
beschrijving
VHDL simulatie
A
A
Place & Route
Y
testbench
B
B
layout
Y
Extractie
vss
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circuit
vss
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Main Interface: GoWithTheFlow
SLS/SPICE simulatie
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ModelSim
n  Overview of all
design objects
n  Interface to
start different
tools
n  simulation of behavior and structural VHDL
descriptions
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Logic synthesis - Synopsys
Placement & Routing
n  Placement of
SoG cells and
hierarchical
cells:
n  madonna
n  row placer
n  Routing of
connections
n  Maps VHDL behavior to VHDL structural
with Sea-of-Gates cells
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Switch-level Simulation
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Rapid prototyping
n  For simulation of “real-time”
behavior an FPGA board can
be used.
n  The behavioral description
(not yet mapped to the SoG
cell library) is translated to
FPGA hardware using the
Quartus software.
n  Allows
simulation
of large
transistor
circuits
n  Extracted
from layout
-> final
verification
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NVIDIA Emulation Farm
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FPGA vs Processor Based Emulators
Today: 3 Billion gates or
more
Grading
Groepscijfer op basis van
n  Originaliteit en complexiteit van het ontwerp
n  Bereikte resultaten m.b.t. simulatie en prototyping
n  Ingeleverde ontwerp bestanden
n  Test plan
n  Eindrapport
n  Presentatie en verdediging
n  Samenwerking binnen de groep
Individueel eindcijfer
n  is groepscijfer g + peer review p, -1 <= p <= 1
From Turner/Bershteyn, ed. Scheffer, CRC press, 2006
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