Introduction to Embedded Data Converters Akira Matsuzawa Tokyo Institute of Technology 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 1 Contents 1. Introduction 2. Characterization of data converters 3. Overview of high-speed A/D converters 4. Overview of high-speed D/A converters 5. Overview of over-sampling sigma-delta data converters 6. Basic design considerations 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 2 1. Introduction • Mixed signal systems – Software defined radio – Digital read channel – Mixed Signal SoC • Progress of ADC and DAC – Power and area – Embedding 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 3 Basic mixed signal system Mixed signal systems basically consist of DSP, ADC, DAC, and pre/post filters. The signals are converted between continuous time and discrete time. Continuous time =Analog AGC Pre Filter Discrete time =Digital ADC DSP Continuous time =Analog DAC Post Filter Clock 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 4 Software defined radio Future wireless systems need powerful ADC and DAC for software defined radio. Future cellular phone needs Multi-standards and multi chips 11 wireless standards!! IMT-2000 RF IMT-2000 BB GSM RF GSM BB Bluetooth RF Bluetooth BB MCU GPS RF GPS BB Power Current Multi-bands and Multi-standards on a single chip Yrjo Neuvo, ISSCC 2004, p.32 Mixer RF filter Future LNA On a chip PA Filter X Filter ADC Frequency Synthesizer X Filter DSP DAC Mixer 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 5 Mixed signal tech. ; Digital read channel DVD Digital storage needs high speed mixed signal technologies. For the reduction of error rate, high speed ADC is the key. Variable Gain Amp. Analog Filter A to D Converter Digital FIR Filter Viterbi Error Correction Data Out 7b 400MHz Voltage Controlled Oscillator Data In (Erroneous) Clock Recovery Pickup signal Analog circuit Digital circuit Data Out (No error) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 6 Mixed signal SoC Mixed signal SoC can realize full system integration for DVD application. Embedded analog is the key. 0.13um, Cu 6Layer, 24MTr CPU2 CPU１ System Controller Pixel Operation Processor Front-End Analog FE +Digital R/C VCO ADC PRML Read Channel Servo DSP Gm-C Filter AV Decode Processor IO Processor Back -End Analog Front End 2006.06.14. Okamoto, et al., ISSCC 2003 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 7 Progress of high-speed ADC High speed ADC can be embedded in CMOS resulting in power reduction. ISSCC 1991 6b, 1GHz ADC 2W, 1.5um Bipolar ISSCC 2000 6b, 800MHz ADC 400mW, 2mm2 0.25umCMOS Pd/ 2N Gsps [mW] Matsuzawa, ISSCC 1991 Pd of high speed CMOS ADCs 10 1/8 1 This Work Sushihara, et al, ISSCC 2000 0.1 ISSCC 2002 World lowest Pd HS ADC 1 10 Conversion rate [x100Msps] 7b, 400MHz ADC 50mW, 0.3mm2 0.18umCMOS Sushihara and Matsuzawa, ISSCC 2002 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 8 Progress of A/D converter; video-rate 10b ADC 1/2000 in Power and 1/200,000 in cost during past 20 years ADC was the bottle-neck for the digital TV and Video systems Technology progress has solved this problem. 1980 1982 1993 Now Conventional product World 1st Monolithic World lowest power SoC Core Board Level (Disc.+Bip) 20W $ 8,000 Bipolar (3um) 2W $ 800 T. Takemoto and A. Matsuzawa, JSC, pp.1133-1138, 1982. 2006.06.14. CMOS (1.2um) CMOS (0.15um) 10mW 30mW $0.04 $ 2.00 K. Kusumoto and A. Matsuzawa, ISSCC 1993. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 9 Power and area reduction of video-rate 10b ADCs Power and area of ADC have been reducing continuously. Currently, ADC can be embedded on a chip Power reduction 2000 1000 500 200 100 50 Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others 20 10 5 Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others 50.0 20.0 10.0 5.0 2.0 1.0 0.5 2 1 1980 1985 1990 1995 2000 2005 2010 Year 2006.06.14. 100.0 Area size (mm2) Power (mW) 10000 5000 Area reduction 0.2 0.1 1980 1985 1990 1995 Year VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 2000 2005 2010 10 Power and area reduction of video-rate 10b ADCs 100.0 50.0 100.0 20.0 10.0 Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others 5.0 2.0 1.0 0.5 0.2 0.1 0.1 0.2 0.3 0.5 0.7 1 2 Process node (m) 3 5 7 10 Area size (mm2) Power/MHz (mW/MHz) 50.0 20.0 10.0 5.0 Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others 2.0 1.0 0.5 0.2 0.1 0.1 0.2 0.3 0.5 0.7 1 2 Process node (m) 5 10 M. Hotta et al. IEICE 2006. June 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 11 Embedding ADC on a CMOS chip CMOS ADC and DAC has been embedded on a CMOS chip. This has realized low cost and low power digital portable AV products. 1993 Model: Portable VCR with digital image stabilizing 6b Video ADC Digital Video filter A. Matsuzawa, JSC, pp. 470-480, 1993. System block diagram 8b low speed ADC;DAC 2006.06.14. 8b CPU VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 12 2. Characterization of data converters • Basic functions of ADC and DAC • Static performance – INL, DNL, monotonicity – Quantization noise • Dynamic performance – – – – SNR, SFDR, THD, SNDR, ENOB Sampling Jitter ERB Glitch • Figure Of Merit • Performances and applications – Needed performances for wireless systems 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 13 Basic functions of ADC Sampling: Sampling the analog signal with accurate timing. Quantization: Express the converted data with certain accuracy. Quantization Voltage Voltage Sampling Time Time ADC Digital 0001 0010 0111 1000 1001 1000 0111 0101 0011 0010 0100 0111 0111 0111 0110 0110 0110 0110 Coding Quantization Sampling Analog Coding CLK 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 14 Static performance INL and DNL are the major static performance indicators of ADC and DAC. DNL: Differential Non-Linearity INL: Integrated Non-Linearity DNL j WidthACTUAL , j WidthIDEAL WidthIDEAL INLj Transfer functionACTUAL , j Transfer fuctionIDEAL , j INLj kj DNL k k 0 DNL j INLj 1 INLj 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 15 DNL and INL DNL profile 2006.06.14. INL profile VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 16 Monotonicity in DAC Binary coded DAC often degrades monotonicity. The monotonicity stands for the qualitative characteristics of data converters of which transfer function keep the monotonic increase or decrease. If the converter can not guarantee the monotonicity, The feedback loop doesn’t work properly and results in backrush. At the change of MSB bit 01111->10000 Binary weight 1/32 Out Out 1/16 1/8 1/2 → 1/2 1/2 Large DNL 1/4 In In 1/4 1/8 1/16 1/32 2006.06.14. Keep monotonic VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. Degrade monotonicity 17 Quantization noise Quantization causes noise Higher SNR needs higher resolution Quantization noise Transfer characteristics Pn /2 e P ( e )de / 2 2 /2 e / 2 2 1 1 P ( e ) ,e 2 0, all other e 2006.06.14. de 2 12 Ps 2 N 1 2 2 Ps 2N 1 SNR Pn 2 P SNRdB 10log s Pn 2 12 2 1.5 22N 6.02 N 1.76 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 18 Dynamic performance Dynamic performance indicates the ratio between signal and noise or distortion. We should use the suitable terms depending upon the type of application. SNR = 10log Signal power T otalnoisefloor power SFDR = 10log T HD = 10log SNDR = 10log Signal power L arg est spurious power T otalharmonic distortion power Signal power Signal power Noise and distortion power SNDR - 1.76 ENOB = 6.02 2006.06.14. Fc=40MHz, fin=4MHz SFDR=49.8dB SNDR=44.9dB, ENOB=7.17-bit 2ndHD=-49.8dB, 3rdHD=-56.7dB VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 19 Sampling jitter effect Sampling jitter is converted to noise. When the input frequency becomes higher, the SNR becomes lower. SNDR ( dB ) 10 log V dV sig V sig dt 1 2f in t 2 120 t SNDR 20 10 t 80 SNDR 50 10 t 60 SNDR 100 10 t SNDR 200 10 t 40 Input signal SNDR 10 106 t 100 6 V 6 6 6 t t 2006.06.14. t0 Time 20 13 1 10 1 10 12 1 10 11 t VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 20 Effective Resolution Bandwidth ERB is the input frequency where the SNDR has dropped 3dB (or ENOB 0.5 bit) 6 SNR ENOB (bit) 3dB (0.5bit) down 5 SNDR 4 ERB 3 100 2006.06.14. 200 Input frequency (MHz) VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 300 21 Glitch Glitch is the spiky signal at code transition. Caused by overlapping of signals This appears within a few psec, However, energy is not negligible. Glitch causes the distortion of signal State 1: [1000]=8 I/2 I/4 I/8 I/16 Pg ,max 2 State 2: [0111]=7 I/2 Pg ,max PQN Glitch I/4 15 I/8 2 N 2 I/16 Tg 2 Tg Ts 2 12 Ts 3 2 2N Current Xg Intermediate: [1111]=15 I/2 2006.06.14. I/4 I/8 8 7 Tg I/16 Time VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 22 Figure Of Merit Figure of merit shows energy efficiency for data conversion. or Power 2 ENOB 2 BW JSSC ,ISSC C ,VLSI 12b 10b ,C IC C ,ESSC C & Products (≧1 0 Bit,≧ 11995-2006 0 M Sps) 10000 1000 Pow er[m W ] Energy Conversion step Power ENOB 2 fs FOM H igh Speed A DC [Sam pling Freq.VS Pow er] 10 bit 0.3 mW / MHz 0.5 pJ / conv 100 12 bit 1mW / MHz 10 0.8 pJ / conv 1 1 10 100 1000 1 2 Bit(Paper) 1 0 Bit(Paper) 1 2 Bit Products 1 0 Bit Products. 10000 Sam pling Freq.[M Sps] 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 23 Performance and application Needed resolution and conversion rate depending upon the application. Conversion Rate (MHz) 1000 500 300 Graphics HDD/DVD Video/ Communication 100 50 30 DVC/DSC/Printer 10 5 Servo Automobile 1 General Purpose 0.5 (µ-Computer) 0.1 Audio 0.05 Meter 6 8 10 12 14 16 Resolution (bits) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 24 Needed SNR for certain BER in wireless system Lower Bit Error Rate in the digital modulation needs higher SNR. 16QAM Q 2A n-PSK BER erfc SNR sin n n-QAM 2 SNR 1 erfc BER 2 1 2 n 1 n 10 I 1 QPSK 0.1 16QAM 256QAM 0.01 BER q( SNR 16) Noise distribution “0” “1” 1 10 BER q( SNR 64) BER q( SNR 256) BER p( SNR 4) 64QAM 1 10 3 4 1 10 5 1 10 6 1 10 7 1 10 8 1 10 9 1 10 BER 2006.06.14. 10 0 10 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 20 SNR 30 40 25 BER requirement The lower the bit error rate the higher the required ADC/DAC resolution. Resolution (quantization noise) affects BER. DAC requirement for QAM 2006.06.14. ADC requirement for digital read-channel VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 26 Signal intensity in wireless system Wireless system has strong unwanted signals. Also, electric circuits generate distortion and noise. Filter A Intensity (dB) Filter B C ADC Far signal > Needed dynamic range to the blocker Adjacent signal B C > Needed SNR Wanted signal Due to aliasing Due to distortion of ADC Thermal noise Frequency 2006.06.14. Amp. A Thermal noise Thermal Noise + Quantization noise VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 27 Needed ADC dynamic range Existence of strong blockers results in the need for high dynamic range ADC. DCS1800 WCDMA Blocker -26dBm signal Wanted signal ADC dynamic range =86dB (14b) -97dBm 15dB Adjacent channel -52dBm -33dB Filter attenuation Wanted signal -93dBm Thermal noise Quantization noise 20dB 8dB -85dB ADC dynamic range =36dB (6b) Quantization noise 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 28 3. Overview of high-speed A/D converters • • • • • • • • Performance and ADC architecture Integrating ADC Successive approximation ADC Flash ADC Sub-ranging ADC Interpolation method Folding ADC Pipelined ADC 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 29 ADC performance and architectures There are many conversion architectures with varying performance parameters. Conversion frequency (Hz) 10G 1G Flash Pipeline 100M Sub-range 10M Multi-bit sigma-delta 1M 100k 10k 4 Successive approximation 6 8 10 Single-bit sigma-delta Integrating 12 14 16 18 20 Resolution (bit) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 30 Integrating ADC Integrating ADC achieves high resolution, but at low speed. Recently it has been used as column-ADC in CMOS imager. -vin S1 R vref Comparator C PhaseⅠ + vx + PhaseⅡ -vin -vin vref vref ・High resolution （20bit and more） ・Very low speed （DC measurement） ・Small DNL ・Can realize zero offset voltage ・Small analog elements and area Going to 0 -> 1, when Vx becomes negative. vx vin 大 vx ( T ) 0 T 2006.06.14. Water clock Time T 0 vin d RC VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. vin T RC 31 Successive-approximation ADC Successive-approximation method is based on a binary search. Comparator Vin S/H b1 b2 b3 VDAC Vref MSB LSB b1 b2 b3 b4 b5b 6 VDAC Vin Bout DAC Binary search VFS Balance Successive-approximation resistor and control logic Vin 1 1 VFS+ VFS 2 4 1 1 1 VFS+ VFS + VFS 2 8 16 1 1 VFS+ VFS 2 8 1 V 2 FS CMPin b1=1 V0 2006.06.14. b1=1 b2=0 b1= b3= 1 b1= b3= b4= 1 b2=0 b2=0 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 32 Charge-redistribution ADC Charge-redistribution ADC draws attention as a suitable ADC in the nanometer CMOS era. Because it needs no OP-Amp, but just needs capacitors and comparator. Vx=0 Q=-2CVin 1) Sampling C C 2 C 4 C 8 C 16 C 16 Binary weighted Capacitor array Vin Vref Vx=-Vin Q=-2CVin 2) Hold C C 2 C 4 C 8 Vin 2006.06.14. C 16 C 16 Vref VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 33 Charge-redistribution ADC 3) Charge redistribution C 2 C Vx=-Vin+Vref/2 Q=-2CVin C 4 C 8 C 16 C 16 If needed Determine from MSB Vin Vref Vref Higher resolution Easy calibration Ultra low power No OP amp Resistor ladder for higher resolution Low conversion rate Needs multi clock 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 34 Flash ADC Flash ADC is very fast, but area and power increase exponentially with resolution. VDD vin Φ R/2 Ultra fast operation: Several GHz No sample and hold Low resolution: <8 bit Large input capacitance difficult to drive Scale + R + R Digital out Vref + + R + R + Encoder R 1 2N 10001 Input voltage 01011 R + R + R/2 2006.06.14. Comparator Vref 0 D1D2D3D4D5 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 35 Sub-ranging ADC Multi-step conversion can reduce the # of comparators. However, it needs high precision comparators. As a result, small power and area. 10 bits : Flash; 2 N 1 1023 N twostep; 2 2 2 1 62 Slide gauge Upper conversion 24 Lower conversion 6 4 16 2 0 8 0 GN D 2006.06.14. Input voltage VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 36 Interpolation method Interpolation can generate accurate intermediate references which are between two references. Thus step sizes are almost equal, even though mismatch voltages are large. Step size Mismatch voltage Step size Small DNL K. Kusumoto and A. Matsuzawa JSC, pp. 1200-1206, 1993. 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 37 Folding ADC Input signal is folded to the compressed signals of which phases are different. Lower bits are obtained by comparing between these folded signals. Low power and small size, yet still high speed. However, not suitable for higher resolution. <10bit vin Folding Circuits Comp Folding Circuits Comp Folding Circuits Comp Folding Circuits Comp Analog signal Digital signal 2006.06.14. ① ② ③ Lower bits Logic Folded signals Upper bits ADC Parallel Folded signals ④ Input signal The signal is compressed →The # of comparators can be reduced VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 38 Folding circuits Output voltage Output voltage Composing the folding characteristics by the summation of currents from differential transistor pairs. VDD VDD V1 V Input voltage in VDD VDD V1 V2 V3 V4 Input voltage Current summation vout Vout Vin V1 V2 V3 V4 V1 vin 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 39 Pipelined ADC Pipelined ADC is the centerpiece of embedded ADCs for many applications, such as digital cameras, digital TVs, ADSLs, VDSLs, and wireless LANs. Suitable for CMOS High resolution(<15bit) Moderate speed(<200MHz) Low power consumption Switched capacitor operation MSB vin LSB M-bit DAP DAP DAP 2nd MSB +Vref DAP -Vref +Vref -Vref 0 S/H Digital Approximater (DAP) ADC (M bit) DAC (M bit) + ×2M +Vref Ｘ２ 0 1 -Vref +Vref Ｘ２ 1 0 1 -Vref Conventional M is 1 or 1.5 Amplifier 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 40 1.5-bit/stage Pipeline ADC Amplification at each stage reduces the input referred thermal noise. 1.5b/stage architecture reduces the requirement for the comparator offset drastically. Transfer characteristics +VR S2 Cf Vi Cs + + VR LATCH V R 4 4 SUB-ADC + S3 -VR +VR - MUX +VR -VR -VR DAC 2X GAIN Unit conversion stage for 1.5-bit/stage pipeline ADC 2006.06.14. Vo Vo 1 C s Cf Vi Ci Vref Cf if 1 C s Cf Vi if 1 C s Cf Vi Ci Vref Cf if Vi VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. Vi Vref 4 Vref 4 Vi Vref 4 Vref 4 41 Pipelining Pipeline action relaxes settling time requirement. Sample & Hold 1st stage 2nd stage Cf Cf - + - + - + Op amp Op amp Op amp + - + - + - Cs Amplify (Hold) Cs Amplify Sample DAC DAC CMP 1st stage 2nd Stage 2006.06.14. Sample CMP Amp. Sample Sample Amp. Amp. Sample Amp. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 42 4. Overview of high-speed D/A converters • Basic two concepts of DAC • Binary method – R-2R based DAC – Capacitor array DAC • Decoder method – Resistor string DAC – Current steering DAC 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 43 Basic two concepts of DAC 1. Binary method Digital 2006.06.14. 1 Di i i 1 2 Analog D3 D2 D1 Digital Small DNL N 1 Small glitch V 2 i Di ana lg Vq Large area i 0 Vref Decoder D3 D2 D1 Binary Weight ckt. Vref N 111 110 101 100 011 010 001 000 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. Switch matrix Not small DNL Large glitch Vana lg Vref Small area 2. Decoder method Analog 44 Binary method R-2R based DAC R-2R resistor ladder can generate binary weighted current easily. Resolution: 12b Large DNL Small area at high resolution Moderate speed Large power consumption A0 A2 A1 2R RF A3 2R 2R vout + 2R Virtual ground -vref R R R 2R I I I v out RF I r A0 r A1 r2 A1 r3 A1 2 2 2 vref Ir 2R 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 45 Capacitor array DAC Binary method Capacitor array DAC is widely used in CMOS technology. Low power and no sample & Hold Q vref C A0 2C A1 4C A2 8C A3 v out Q 16C Reset 8C Ai= 0 or 1 16C Virtual ground 4C 2C + C vout 16C vref Q Enable 8C 4C A3 2C A2 + C A1 vout A0 vref 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 46 Decoder method Resistor string DAC Decoder method can realizes small DNL, however needs large area at high resolution. Vref 111 110 101 Resolution limit: 10b Good DNL Low speed Small glitch R R R R Vout 100 R + 011 R 010 001 000 R large parasitic capacitance: 2N Digital value R Decoder 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 47 Current steering DAC Decoder method Widely used for high speed DAC. High speed, -- 1 GHz Resolution – 14 b Small DNL Small glitch Graphics, communications, etc. Conventionally large area VDD Vout Vout Di=1 Di Row decoder Di Bias Di=0 Current source Current cell with switch 2006.06.14. R Column decoder VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 48 5. Overview of over-sampling sigma-delta data converters • Sigma-delta modulation method – – – – – – – 2006.06.14. Over sampling Noise shaping Sigma-delta modulator SNR Higher order system Feed forward and feed back compensation MASH (Multi-stage noise shaping) VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 49 Sigma-delta ADC, DAC Sigma delta ADC and DAC are widely used in high resolution (14b-24b) and not high speed ( <1MHz) applications. Sigma delta ADC Sigma delta DAC Integrator AVDD Comparator x(n) + z-1 + Digital Filter 1bit DAC Analog DAC out Digital C Integrator vin Digital Signal Processing LPF Φ1 C Φ2 Φ1 Φ2 + Implemented in CMOS, easily. vref 2 2006.06.14. vref 1bit DAC 2 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 50 Over sampling Over sampling can reduce effective quantization noise. Band limiting filter x(n) y1(n) Δ H(f) y2(n) Quantization noise power Pe fs /2 fs /2 Se2 ( 1 2 2 f b f ) H ( f ) df df f b 12 f 12 s fs 2 fb 2 he(x) H(f) -fs/2 -fb fb 2 1 12 OSR OSR fs 2 fb Total noise power is invariant f fs/2 In-band noise Reduction of bandwidth by filter → Reduction of effective noise power 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 51 Noise shaping Spectrum of quantization noise is shaped by differentiator. In-band noise can be reduced. Output signal Input signal Integrator 1. 2. Signal intensity Low pass filter 1. Differentiator Quantizer 4. 3. Noise 2. High pass filter 3. 4. Noise Noise BW fS 2 f Signal: Low pass filter x High pass filter Flat fS 2 In-band noise is reduced Quantization noise: High pass filter Lower in low frequency The spectrum of the quantization noise increases with frequency increase. Only quantization noise is shaped in frequency characteristics 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 52 Sigma-delta modulator Sigma-delta modulator shapes the frequency characteristics of the quantization noise The signal will overflow Integrator Differentiator Quantizer + X(z) Y(z) + Q(z) z 1 z 1 X( z ) 1 z 1 Y ( z ) X ( z ) (1 z 1 )Q( z ) Equivalent transform Output Input signal signal Differentiator Integrator X(z) + + z 1 Y(z) Quantizer Q(z) X Q Z 1 z 1 Quantization noise Differentiator (High pass filter) Y ( z ) X ( z ) (1 z 1 )Q( z ) No overflow 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 53 Generic expression of sigma-delta modulator We can use not only LPF but also BPF and complex BPF. This gives us an excellent opportunity for wireless applications. X(z) Quantizer Filter Input signal + H(z) Q(z) Output signal Y(z) z 1 H( z ) 1 Y( z) X( z ) Q( z ) 1 1 1 H( z )z 1 H( z )z STF (Signal Transfer) Ex. H( z ) 1 1 z 1 STF ( z ) 1, No filter 2006.06.14. NTF (Noise transfer) NTF ( z ) 1 z 1 High pass filter VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 54 Noise power in sigma-delta modulator fb Lth order filter 0 Y ( z ) X( z ) 1 z Q( z ) 1 L SNR = 113.8dB -20 -40 f) -60 dBFS h q2 ( 2 12 f s -80 Digital Filter -100 Nq fb 2L fb z e j 2 f h q2 ( f ) 1 z 1 fs=26MHz -120 / fs -140 fb 2 fb 12 f s 2006.06.14. j 2 f fs 2L 2 1 df 2 3 2 L 1 OSR 0 2 4 2 L 1 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 6 8 Frequency (MHz) 10 12 55 2nd order sigma-delta ADC Q( z ) X( z) ++ - Y(z) ++ 1st order SD ADC 1 z DAC DAC Q1( z ) 1 z 1st order SD ADC Q( z ) X( z) ++ - ++ ++ z1 Y(z) ++ DAC DAC Quantizer is replaced by 1st order SD ADC z1 z1 DAC DAC z1 2nd order SD ADC Y ( z ) X ( z ) 1 z 1 Q1( z ) Q1( z ) 1 z 1 Q( z ) Y ( z ) X( z ) 1 z 2006.06.14. Q( z ) 1 2 X( z) ++ DAC DAC 1 1 1 z ++ - 1 1 1z Y(z) 2 DAC DAC VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 56 Multi bit sigma-delta ADC X( z) ++ a1 1 1 1 z DAC DAC ++ a2 1 1 1z 1 1 1 z ++ - - a3 DAC DAC DAC DAC ++ 1 1 1z Y(z) a4 DAC DAC Feedback type NTF ( z ) (1 z 1 ) 4 X( z) ++ - 1 1 1 z b1 1 1 1z b2 1 1 1z b3 1 1 1z b4 Y(z) ++ DAC DAC Feedforward type 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 57 Dynamic range of sigma-delta ADC Higher order SD modulator seems effective to increase the dynamic range. However it is not easy, because of instability, signal saturation, and thermal noise. Dynamic Range (dB) 2 3 N OSR DR 2 1 2 L 1 2 5th 200 180 160 140 120 100 80 60 40 20 0 2 L 1 4th 3rd n=1bit 2nd 1st 1 10 100 1000 OSR 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 58 Noise-shaping characteristics Higher order sigma-delta modulator can realize higher dynamic range, theoretically. 0 0 SNDR = 99.5dB -20 SNR = 100.1dB -20 -60 dBFS -80 1st Dynamic Range (dB) -40 order 20dB/dec -100 -120 2nd order -140 40dB/dec -160 -80 10 4 10 5 10 6 10 5th order, 1bit 100dB/dec -100 -120 -140 In-band OSR=64 200kHz Thermal noise -180 fs=26MHz Frequency (Hz) 2006.06.14. -60 -160 -180 -200 3 10 -40 7 -200 3 10 10 4 10 5 6 10 7 10 Frequecy (Hz) VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 59 Cascade (MASH) sigma-delta modulator Cascaded SD modulator can realize higher order noise shaping without stability issues. However, high dynamic range is difficult, due to severe mismatch requirement. Q1( z ) X( z) ++ - 1 1 1 z ++ 2 1 1 1z Y1 Q1 DAC + Q1( z ) H1 ( z ) Y1( z ) ++ - Q2 ( z ) Y2 ( z ) 1 1 1z H2( z ) + Y(z) DAC 2 Y1( z ) X( z ) 1 z 1 Q1( z ) H1( z ) 1 Y2 ( z ) Q1( z ) 1 z 1 Q2 ( z ) H2 ( z ) 1 z 1 2 2 2 3 Y ( z ) Y1H1 Y2 H2 X ( z ) 1 z 1 Q1( z ) 1 z 1 Q1( z ) 1 z 1 Q2 ( z ) 3 Y ( z ) X ( z ) 1 z 1 Q2 ( z ) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 60 6. Basic design considerations • Accuracy – Current mismatch and DAC accuracy – VT mismatch – Capacitor mismatch • Comparator – Offset compensation • Op-Amp – Gain and GBW – kT/C noise 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 61 Current mismatch and DAC accuracy Larger resolution requires smaller mismatch. I i1 I i0 I i2 I i2 N 1 INL yield 0.1 10% 50% ( I ) I 1 2C 2 N 90% sigma( 3.0 N) sigma( 2 N) sigma( 1.3 N) 99.7% 0.01 sigma( 0.8 N) N: resolution C: constant determined by INL yield 1 10 2006.06.14. 3 6 8 10 N 12 14 Van den Bosch,.. Kluwer 2004 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 62 VT mismatch Larger gate area is needed for smaller VT mismatch. Technology scaling reduces VT mismatch if the gate area is equal. 100 VT ( mV ) VT Tox LW VT( LW) 10 0 VT( LW) 1 VT( LW) 2 1 0.4um Nch 0.13um Nch Boron, w. Halo 0.13um Nch In w/o Halo* 0.1 1 10 100 1 103 LW LW ( m 2 ) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 63 Mismatch current and transistor size Smaller mismatch requires larger L and W. I ds I ds I ds I ds I ds I ds 2006.06.14. W K' Vgs VT L I ds I I ds W VT ds K ' VT K ' W L L W 2 VT K' L V gs VT K' W L 2 Mismatch 2 VT K ' K' AVT LW AK ' LW W 1 1 L A WL W W 2 L2 L 2 4 K' AVT AK2 1 2 1 2 AWL 2 2 WL L I W L ds V gs VT 2 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. I ds W K' L 64 Capacitor mismatch Smaller capacitor mismatch requires larger capacitance C 6 104 (3 ) C C ( pF ) Coefficient depends on the Fab. Typical MIM capacitor 10bit: 0.4pF 12bit: ４pF 14bit: 40pF 10bit, ¼ LSB C (3 ) C 12bit, ¼ LSB 14bit, ¼ LSB Capacitance (pF) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 65 CMOS comparators There are many types of comparator circuits 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 66 Low power CMOS comparator A CMOS comparator is low power because of no need of static current. No static current Differential comparison Interpolation action High speed CLK T.B.Cho., et al., J.S.C., Vol.30, No.30, pp.166-172, Mar. 1995. VDD Interpolation action m11m9 m10 m7 W m6 Vin2+ Vin1 - m1 m2 W1 W 1 Vin1 Vth 2 Vin2 Vth Out+ G1 K p L L Out- W W G 2 K p 1 Vin1 Vth 2 Vin 2 Vth L L m8 m5 Vin1+ m12 W2 Vin2m3 m4 W1 W2 m n n : m m then, m n Vin1 nVin 2 m n Vin1 nVin 2 if W1 : W2 VSS 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 67 Design rule and Speed in Comparator Gain bandwidth (=Speed) is inversely proportional to the L2 (channel length). Technology scaling is still effective to increase the comparator speed, if we don’t take care of the signal dynamic range. gm I sin k 2 2 2 WC j Cox LW 2 WC j Cox LW Veff 3 3 I sin k R Cox W 2 R Isink L 2 Veff R Cox GBW L R Isink Veff 2 Cj 2L2 3 k 20 Relative bandwidth GBW 15 10 5 0 0.1 0.2 0.3 0.4 0.5 Feature size ( m) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 68 Offset compensation Two ways for suppressing offset voltage. Store the offset voltage in capacitors and subtract it from the signal. Feedback= High gain type Vin1 Vin2 + Va A - + Vo Latch Va VosA ( A ) Vo Va Vout Vo Va CLK A VosA 1 A VosA: Offset of the amplifier a) Offset cancel at input nodes VosL: Offset of the latch Feed forward =Low gain type Vin1 Vin2 + A - + Latch Vout Vos _ in Vosl A CLK b) Offset cancel at output nodes 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 69 Operational amplifier Higher resolution requires higher open loop gain. Higher conversion frequency requires higher closed loop GBW. Sampling DC gain Cf Vn Vin G error - + Op amp Amplify Cs Cf 1 G N:ADC resolution M：Stage resolution G (dB ) 6N 10 Vout - + Vn C 2 p Cf 1 N M 1 G 2 + - Vn 1 G 1 C 2 p Cf for 1.5b pipeline ADC Op amp + - Vn Closed loop gain-bandwidth Cp Cs VDAC GBW_ close Equivalent circuit Cf gmβ N fc 2πC L 3 β 1 Cs 2006.06.14. Cpi gm s 1 ωp 2 Cpo RL COL Cf C f Cs C pi CL C po CoL VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. C f Cs C pi C f Cs C pi 70 kT/C noise Larger SNR requires larger capacitance and larger signal swing. Low signal swing increases required capacitance. nkT φ vn2 n: configuration coefficient C 2 CVFS SNR( dB ) 10 log 8nkT vn v out CL 95.918 100 VFS=5V VFS=3V n=2 90 14bit VFS=2V SNR (dB) SNRC 1 2 C R SNRC 2 2 C CL VFS=1V 80 12bit SNRC 3 2 C SNRC 5 2 C 70 10bit v n2 4kTR 1 1 CR 2 d kT 2 C 60 51.938 50 0.1 0.1 0.1 1 1 10 C 10 100 100 100 Capacitance (pF) 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 71 Basic design consideration Very tough tradeoffs, so let’s keep up the design effort. Small mismatch Voff C 1 or N C VFS 2 Solutions Pipeline, Parallel Increase Capacitance C 1 1 1 or Voff C C LW Cg C 2 2N 2) Redundancy 3) Error compensation 4) Circuit design However, kT/C issue remains 2 SNR CVsig 22N Results in Decrease speed and Increase Power g g I I f s GBW m 2mN GBW d 2dN C 2 C 2 Pd V dI d f s C f s 2 2 N I 2N f s 2dN P f 2 d s 2 2006.06.14. 1) Architecture 2N C Vsig 2 Solutions 1) 2) Increase signal swing Increase OSR SNR OSR VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 72 Acknowledgement • The author thanks Mr. T. Matsuura from Renesus for some slides provision. 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 73 Study-aid books • B. Razavi, “Data conversion system design,” IEEE press. • P. E. Allen and D. R. Holberg, “ CMOS Analog Circuit Design,” 2nd Edition, OXFORD University Press. • D. A. Johns and K. Martin, “Analog integrated circuit design,” John Wiley & Sons. • R. J. Baker, “ CMOS mixed-signal circuit design,” IEEE Press. • R.van de Plassche, “CMOS Integrated Analog-to-Digital and Digitalto-Analog Converters,” 2nd Edition, Kluwer Academic Publishers. • M. Gustavsson, J. J. Wikner and N. N. Tan, “CMOS data converters for communications,” Kluwer Academic Publishers. • C. Shi and M. Ismail, ”Data converters for wireless standards,” Kluwer Academic Publishers. • A. Rodriguez-Vazquez, F. Mederio, and E. Janssens, “CMOS Telecom Data Converters,” Kluwer Academic Publishers. 2006.06.14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 74
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