Lecture 20: Circuit Families

Lecture 20:
Circuit
Families
Outline
 Domino gate
 Dual-Rail Domino
 np-CMOS (Zipper)
Circuit Families
CMOS VLSI Design 4th Ed.
2
Domino Gates
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs

Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C

Y
Z
dynamic static
NAND inverter

A
B
Circuit Families


W
X
H
C
CMOS VLSI Design 4th Ed.
Y
H
Z
=
A
B

X
Z
C
3
Domino Optimizations
 Each domino gate triggers next one, like a string of
dominos toppling over
 The dynamic output is monotonically falling during
evaluation, so the static inverter output is
monotonically rising.
 Therefore, the static inverter is usually a HI-skew
gate to favor this rising output.
 Gates evaluate sequentially but precharge in parallel
 Thus evaluation is more critical than precharge
Circuit Families
CMOS VLSI Design 4th Ed.
4
Domino Optimizations


In general, more complex inverting static CMOS gates such as NANDs or
NORs can be used in place of the inverter [Sutherland99]. This mixture of
dynamic and static logic is called compound domino.
For example, an 8-input domino multiplexer built from two 4-input dynamic
multiplexers and a HI-skew NAND gate. This is often faster than an 8-input
dynamic mux and HI-skew inverter because the dynamic stage has less
diffusion capacitance and parasitic delay.

S0
S1
S2
S3
D0
D1
D2
D3
H
Y

Circuit Families
S4
S5
S6
S7
D4
D5
D6
D7
CMOS VLSI Design 4th Ed.
5
Dual-Rail Domino
 Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
 Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
Y_h
Y_l
Meaning (f=?)
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
Circuit Families

Y_l
inputs
f
Y_h
f

CMOS VLSI Design 4th Ed.
6
Example: AND/NAND
 Given A_h, A_l, B_h, B_l
 Compute Y_h = AB, Y_l = AB
 Pulldown networks are conduction complements

Y_l
A_h
= A*B
A_l
B_l
Y_h
= A*B
B_h

Circuit Families
CMOS VLSI Design 4th Ed.
7
Example: XOR/XNOR
 Sometimes possible to share transistors

Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h
A_h
= A xor B

Circuit Families
CMOS VLSI Design 4th Ed.
8
Dual-Rail Domino: Example
 XOR/XNOR3
Circuit Families
CMOS VLSI Design 4th Ed.
9
Leakage
 Dynamic node floats high during evaluation
– Dynamic value will leak away over time
 Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper

A
1 k
X
H
Y
2
2
Circuit Families
CMOS VLSI Design 4th Ed.
10
Charge Sharing
 Dynamic gates suffer from charge sharing


A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
Circuit Families
CMOS VLSI Design 4th Ed.
11
Charge Sharing
 Dynamic gates suffer from charge sharing


A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
CY
Vx  VY 
VDD
C x  CY
Circuit Families
CMOS VLSI Design 4th Ed.
12
Secondary Precharge
 Solution: add secondary precharge transistors
– Typically need to precharge every other node
 Big load capacitance CY helps as well

Y
A
secondary
precharge
transistor
x
B
Circuit Families
CMOS VLSI Design 4th Ed.
13
np-CMOS (Zipper)
CLK
Mp
!CLK
11
10
Out1
In4
In1
In2
Me
PUN
In5
PDN
00
01
In3
CLK
!CLK
Me
Mp
to other
PDN’s
Out2
(to PDN)
to other
PUN’s
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
Circuit Families
CMOS VLSI Design 4th Ed.
14
Power
 Domino gates have high activity factors
– Output evaluates and precharges
• If output probability = 0.5,  = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have  = 1
 Leads to very high power consumption
Circuit Families
CMOS VLSI Design 4th Ed.
15
Domino Summary
 Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS
– But many challenges:
• Monotonicity, leakage, charge sharing, noise
 Widely used in high-performance microprocessors in
1990s when speed was king
 Largely displaced by static CMOS now that power is
the limiter
 Still used in memories for area efficiency
Circuit Families
CMOS VLSI Design 4th Ed.
16

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