Responding to TAT Improvement Challenge through

Responding to TAT Improvement
Challenge through Testbench
Configurability and Re-use
Akhila M, Kartik Jain, Renuka Devi,
Mukesh Bhartiya
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Agenda
• Motivation
• Generic AMBA based SoC Template
• Key Areas to Target for Re-usability and Reconfigurability
• Recommended Techniques for faster TTM
• Results
• Conclusion
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Motivation
Complex SoCs demanding faster TTM
-- New and challenging IPs integration
-- Multiple SoC churn outs with few extra features added
-- Demands good verification coverage and corner case testing
10%
35%
Testbench Development
Testplan Creation and
Running tests
40%
Debug
15%
Others
*source:http://blogs.mentor.com/verificationhorizons/blog/author/hfoster/page/2/
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Proposed Pre-Silicon Validation
Methodology
Reusability of IP/block level tests at SoC level
Reconfigurable verification environment for project
variations
Reduce test-bench modification efforts when
absorbing changes
REUSE-RECONFIGURE-REDUCE !!!
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Generic AMBA based SoC Template
AMBA VIP/Wrapper
UVM
sequencer
Controls all
the
sequencers
SoC Specific IP(s)
Core
DMA
BASE UVM ENV
I2C VIP
I2S VIP
Primary fabric – AHB/AXI
UART VIP
GPIO VIP
I2S
I2C
Memories
Low speed fabric - APB
GPIO
UART
DATA Checkers
DATA
Checker
Hooked to all IFs
DATA Checker
Hooked to all IFs
Hooked to all IFs
Coverage Module
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Key Areas to Target for
Re-usability and Re-configurability
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Fabric VIP Configuration
Backbone of Verification Environment
• Architectural updates:
Change in # and type of layers
Change in # of peripherals
Hierarchy changes
Access control changes
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Address map changes
Address/data width changes
Core Testbench Components
(Base sequences, Data checkers)
• Dependencies on VIPs
– VIP sequences, data checkers and base components and their
extensions tightly coupled to transaction type
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Core Testbench Components
(Base sequences, Data checkers)
VIP AXI SEQ
???
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Block Level Tests
• Re-run block level tests in UVM – BINGO!!!
• IPs developed in different language(s)
– Adoption of System-C by designers
• IP tests have different execution phases
– Block level tests and system level tests have to be
synchronized
SC_MAIN() {
config
send data
new config …
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DUT
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UVM run_test()
Phases
Sequences
Recommended Techniques for
Faster TTM
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Reconfigurable Wrappers for Main fabric VIP
Encapsulates VIP Config Class details from users
• Encapsulates VIP Config Class details from users
Function: set_new_layer
Layer type, ID Name, # Master, Slaves, Clock/ Reset mode
agent_data_holder_st
store agent configs
layer_data_holder_st
store layer configs
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Loop for all agents / layer
Function: register_layer_master/slave
Agent specific parameters
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VIP Configuration:
Num of agents
Data/ Addr width configs
AHB_Lite/ APB3/ APB4
configs
Master-Slave clock/ reset
mode configs
Active/ Passive configs
Agent addr mapping
AMBA Monitor hook-ups
Other configs
Easy Configuration of External
Interfaces
AMBA VIP CONFIGURATION
int layer_master
[0:`NO_OF_AMBA_LAYERS-1]
int layer_slave
[0:`NO_OF_AMBA_LAYERS-1]
int layer_clock_mode
[0:`NO_OF_AMBA_LAYERS-1]
int layer_reset_mode
[0:`NO_OF_AMBA_LAYERS-1]
int set_xaction_mon
[0:`NO_OF_AMBA_LAYERS-1]
= {4,2,1};
= {5,1,1};
= {1,1,1};
= {1,1,1};
= {1,1,1};
OTHER VIP CONFIGURATION:
int uart_active[0:`NO_OF_UART_INSTANCES-1]
= {1,1};
int
handshake_type[0:`NO_OF_UART_INSTANCES-1]
= {0,0};
int data_width[0:`NO_OF_UART_INSTANCES-1]
= {8,8};
int stop_bit[0:`NO_OF_UART_INSTANCES-1]
= {1,1};
int parity_type[0:`NO_OF_UART_INSTANCES-1]
= {1,1};
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Generic Sequences
Independent of VIP Transactions
 All Sequences extended from UVM sequence
– Sequencer casting just before driving UVM item, NOT at virtual
sequence level
MY SEQ L1
UVM SEQ
MY SEQ L2
`my_uvm_do_on
(AHB/ AXI seqr, seq/
item)
MY SEQ
L11
MY SEQ
L12
MY SEQ
L21
Map
Item
to VIP
Item
• Tie item/ sequence to UVM seqr
• Save actual seqr pointer
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VIP AHB
SEQ
VIP AXI SEQ
Generic Data Checkers
Independent of VIP Transactions
• Configurable end-to-end data checker working on
customized transaction type
– Performs data sanity on peripheral interface
– Handles on-the-fly reset/ abort conditions, selectively turning
off checker on any given interface, applying byte-mask
TX VIP Xaction
Map to Checker Xaction
PASS/ FAIL
RX VIP Xaction
Map to Checker Xaction
Thru Analysis ports
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Apply any byte masks, UVM event
controls
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HDL Independent Verification Flow
• Pre-requisites to switch between System-C or UVM driver.
SystemC model
• Loosely timed (LT)/
Approximately timed(AT)/ Pin
accurate models(PA)
SystemC
Function Reuse
• Divide System-C tests into
Multiple Function calls
Handshake
• DPI Calls / Assertion of
SCSV Interface Signals.
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Results
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Improvement in Time to First Test
14
12
10
Weeks
8
Project1
6
Project 2
4
2
0
Project1
Project 2
Configurable wrappers were used for VIPs
and System-C driver was integrated
Improvement in Overall Run Time
Avg Wall Clock Time in Mins
18
15
12
9
Project1
6
Project2
3
0
Similar peripheral tests
Project1: One copy of each VIP license checkout per run
Project2: Only 1 license checkout per run, if compiled with proper defines
Conclusion
• Re-use  Prior engagement with IP team to
integrate pin accurate model renders test re-use
option
• Re-configure  Configurable VIP wrappers for fabric
and external interfaces
• Reduce  Decoupling components’ dependencies
on VIP transactions reduces rework.
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Thanks
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