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Cadence Design System: Brief Introduction
Cadence Design Systems Inc. is an American electronic design automation (EDA) software and
engineering
services
company,
founded
in
1988
by
the
merger
of SDA
Systems and ECAD,Inc. The company produces software for designing integrated circuits also
known as chips, systems on chip(or SoCs) and printed circuit boards.
Cadence's product offerings are targeted at various types of design and verification tasks which
include:

Virtuoso Platform - Tools for designing full-custom integrated circuits; includes schematic
entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical
verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and
standard-cell designs, but also memory and FPGA designs.

Encounter
Platform
-
Tools
for
creation
of digital integrated
circuits.
This
includes floorplanning, synthesis, test, and place and route. Typically a digital design starts
from Verilog netlists.

Incisive
–Tools
Platform
verification
of
Includes formal
RTL
including
verification, formal
Verilog,
for simulation and functional
VHDL and System
equivalence
C based
checking, hardware
models.
acceleration,
and emulation.

Palladium series - Accelerators and emulators for hardware and software co-verification and
system-level verification.

Design IP: Cadence provides design IP targeting areas including memory (DRAM), covering
DDR1, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Wide I/O; storage (nonvolatile memory), covering NVM Express and NAND Flash controller and PHY; and highperformance interface protocols such as PCI Express Gen3, 40/100G Ethernet, and USB 2
and USB 3.

Verification IP (VIP) Cadence provides the broadest set of commercial VIP available with
over
30
protocols
in
its
VIP
Portfolio.
They
include AMBA, PCI
Express, USB, SATA, OCP, SAS, MIPI and many others. Cadence VIP also provides the
unique Compliance Management System
verification.
(CMS) to
automate protocol
compliance

Integration Optimized IP (Design IP) Cadence offers Vertically Integrated IP, inclusive of
Digital Controller, Serdes Layer, and Device Driver. Protocols supported include USB,
DDR, PCI-Express, 10G-40G Ethernet, and On Chip Bus Fabric.

Allegro Platform - Tools for co-design of integrated circuits, packages, and PCBs.

OrCAD/PSpice - Tools for smaller design teams and individual PCB designers.

Sigrity technologies - Tools for signal and power verification for system-level signoff
verification and interface compliance.
In addition to EDA software, Cadence provides contracted methodology and design services as
well as silicon design IP, and has a program aimed at making it easier for other EDA software to
interoperate with the company's tools.
FIGURE 1: CADENCE LIBRARY MANAGER WINDOW
The left column is a list of the current libraries. From these libraries analogLib is of most
importance. This library contains all the components used during vlsi circuit design and it will be
used the most.
Left click on analog Lib in the library browser. Left click on nmos4 to display the cell views of
the nmos transistor design. You should be able to see several different cell views. The cell views
contain the following information:
Symbol - contains the symbol representation of the schematic.
CdsSpice, HspiceS, Spectre, spectreS–contain spice information for the element.
Feel free to look at any of the cell views. To do this, click center and hold on the cell view and
choose read or you can double click on the particular cell view of interest. A window will open
showing the contents of that particular window. In different cells, you may encounter the
following cell views:
abstract- contains an abstract representation of the layout for use by Cadence place and route
software.
extracted- contains layout connectivity for use by verification programs.
layout- contains the silicon-level representations of the transistors and wiring.
schematic- contains the logical design of the device.
behavioral– contains the VHDL description of the cell
GENERATING NETLIST IN CADENCE
The generate netlist in cadence the following steps need to be done.
1. Create a directory in the LINUX environment
2. Invoke cadence license.
3. Invoke the library.
4. Create .g files to write the program and then save it.
5. Run rc compiler to get inside the tool
6. Do few of the steps like synthesize to mapped and generic.
7. Write the command to generate netlist.
8. Type exit to come out of the tool.
9. The netlist file will be in the LINUX command window.
The final Netlist file look the one given below.
FIGURE 2: CADENCE NETLIST FILE
Although Cadence can provide netlist information at gate-level in a text format, the license cost
of cadence is very high. On the other hand, we have used Xilinx Student version software, which
is available for free. The ngc file produced by Xilinx is then converted into edif file format and
finally run through various programs as described above to give the gate-level information.
The steps are shown in the flow chart and described below.
XILINX: BRIEF INTRODUCTION
Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic
devices. It is known for inventing the field programmable gate array (FPGA) and as the
first semiconductor company with a fabless manufacturing model.
XILINX ISETM Design Tools
Xilinx ISETM is the design tool provided by Xilinx. Xilinx provides a free version of this tool
called Web packTM which would be virtually identical for our purposes.
There are four fundamental steps in all digital logic design. These consist of:
1. Design – The schematic or code that describes the circuit.
2. Synthesis – The intermediate conversion of human readable circuit description to FPGA code
(EDIF) format. It involves syntax checking and combining of all the separate design files into a
single file.
3. Place & Route– Where the layout of the circuit is finalized. This is the translation of the
EDIF into logic gates on the FPGA.
4. Program – The FPGA is updated to reflect the design through the use of programming
(.bit) files.
Test bench simulation is in the second step. As its name implies, it is used for testing the design
by simulating the result of driving the inputs and observing the outputs to verify your design.
ISE has the capability to do a variety of different design methodologies including: Schematic
Capture, Finite State Machine and Hardware Descriptive Language (VHDL or Verilog), although
ISE has its own simulation engine.
An example in Xilinx using Verilog code
We have taken a random example, where a full adder and 2 multiplexer are used to show the 3
types of LUT (look up table) configuration. LUTs can be of 2, 3, 4 input configuration with 1
output. In this example the three inputs x, y and z are given to a full adder. The output sum of the
full adder is connected to one of the multiplexer. The signal reset acts as a select line for both the
multiplexer. When select is 0 the multiplexer will give the output as sum otherwise the output
will be 0. Like the carry output of the full adder is connected to the other multiplexer. If reset is 0
then it will give output as carry, otherwise 0. X and Y are AND ed and X, Y and Z are ORed.
CODE:
module main(x,y,z,rst,q,out,out1,out2,out3);
inputx,y,z,rst,q;
output out,out1,out2,out3;
wires,c;
f_adder f_addr1(x,y,z,s,c);
mux1 mux_sum(rst,s,out);
mux1 mux_carry(rst,c,out1);
and(out2,y,x);
or(out3,x,y,z);
endmodule
modulef_adder(
input a,
input b,
inputcin,
output sum,
output carry);
assign sum = a ^ b ^ cin;
assign carry = ((a ^ b)&cin) | (a & b);
endmodule
module mux1(rst,q1,mux_out);
input rst,q1;
outputmux_out;
regmux_out;
always @(rst or q1)
begin
if(rst==1'b1)
mux_out<= 0;
else
mux_out<= q1;
end
endmodule
The Verilog code can be written in Xilinx is shown in the figure below.
FIGURE 3: VERILOG CODE
After the code is Synthesized, we get two schematic views of the circuit. Namely,
1. RTL schematic
2. Technology schematic
RTL SCHEMATIC VIEW OF THE EXAMPLE
The block we see in the below screenshot is a result of the Verilog code as given in the example.
Here, q, rst, x,y, z are the inputs to the block and out, out1, out2, out3 are output of the block.
FIGURE 4: FIRST RTL SCHEMATIC VIEW FOR THE ABOVE VERILOG CODE
When we double click on it, we get the inside view of block as shown below:
The below screenshot contains one full-adder block, two multiplexers, one two-input AND gate
and a 3-input OR gate.
The figure 5 is also showing the inter-connections between various blocks.
FIGURE 5: INSIDE VIEW OF RTL SCHEMATIC
Now double click on the full-adder block, we get the inside view of the full adder as shown in
the next screenshot.
Here a , b and cin are inputs to the circuit and carry and sum are outputs.
FIGURE 6: INSIDE VIEW OF THE FULL ADDER BLOCK
FIGURE 7: INSIDE VIEW OF THE MUX_CARRY
FIGURE 8: INSIDE VIEW OF THE MUX_SUM
XILINX store all RTL schematic information in a file with file extension of .ngr
TECHNOLOGY SCHEMATIC VIEW OF THE EXAMPLE
FIGURE 9: FIRST TECHNOLOGY SCHEMATIC VIEW OF THE EXAMPLE
When we double click on it, we get the inside view of the LUT (Look Up-Table) as shown
below:
FIGURE 10: INSIDE VIEW OF THE TECHNOLOGY SCHEMATIC
In the above diagram, there are four LUTS.
1. LUT4_4114
2. LUT4_5440
3. LUT2_8
4. LUT3_FE
LUT4 refers that there are 4 inputs to the LUT. Similarly, LUT2 and LUT3 refers there are 2 and
3 inputs the LUTs respectively.
The Initials of the LUTs’ i.e. 4114, 5440, 8 and FE are the values that we get from the truth table
for the respective LUTs.
Taking the example of LUT4_4114
I3
I2
I1
I0
0
INIT
0
0
0
0
0
4
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
4
TABLE NO. 1: TRUTH-TABLE OF LUT4_4114
Output (O) is readfrom bottom of the table. That means first 4 comes for the combination.
1100
1101
1110
1111
0
0
1
0
Double-clicking on the LUT4_4114 will give the inside view of the LUT as shown in Figure 9.
FIGURE 11: INSIDE VIEW OF THE LUT4_4114
FIGURE 12: INSIDE VIEW OF THE LUT4_5440
FIGURE 13: INSIDE VIEW OF THE LUT2_8
FIGURE 14: INSIDE VIEW OF LUT3_FE
The technology Schematic view information of the example is stored by the XILINX in a file
with the extension of .ngc
Now, .ngc file format is not in the text file format. To make it in a readable text format, we need
to convert the file format into EDIF file extension.
We have to note that XILINX student edition does not provide any Gate-Level
information unlike Cadence.
ABOUT THE EDIF FILE
EDIF (Electronic Design Interchange Format) is a vendor-neutral format in which to store
Electronic netlists and schematics. It was one of the first attempts to establish a neutral data
exchange format for the electronic design automation (EDA) industry. The goal was to establish
a common format from which the proprietary formats of the EDA systems could be derived.
When customers needed to transfer data from one system to another, it was necessary to write
translators from one format to other. As the number of formats (N) multiplied, the translator
issue became an N-squared problem. The expectation was that with EDIF the number of
translators could be reduced to the number of involved systems.
The general format of EDIF involves using parentheses to delimit data definitions, and in this
way it superficially resembles Lisp. The basic tokens of EDIF 2.0.0 were keywords
(like library, cell, instance, etc.), strings (delimited with double quotes), integer numbers,
symbolic constants (e.g. GENERIC, TIE, RIPPER for cell types) and "Identifiers", which are
reference labels formed from a very restricted set of characters. EDIF 3.0.0 and 4.0.0 dropped the
symbolic constants entirely, using keywords instead. So, the syntax of EDIF has a fairly simple
foundation.
STEPS TO GENERATE EDIF FILE
1. Open command prompt
2. Change directories and go to the folder where the ngc file is present.
3. Write the following code as shown in the screenshot below and press enter.
FIGURE 15: COMMAND PROMPT VIEW TO MAKE EDIF FILE FROM NGC FILE
EDIF file of the above example:(edif main
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2013 7 26 10 49 39)
(program "Xilinx ngc2edif" (version "K.31"))
(author "Xilinx. Inc ")
(comment "This EDIF netlist is to be used within supported synthesis tools")
(comment "for determining resource/timing estimates of the design component")
(comment "represented by this netlist.")
(comment "Command line: main.ngcmain.edf ")))
(external UNISIMS
(edifLevel 0)
(technology (numberDefinition))
(cell LUT2
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port I0
(direction INPUT)
)
(port I1
(direction INPUT)
)
(port O
(direction OUTPUT)
)
(property TYPE (string "LUT2") (owner "Xilinx"))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "8") (owner "Xilinx"))
)
)
)
Port I0 and port I1, which are highlighted are inputs to the LUT2. Port O is output of LUT2.
cell LUT3
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port I0
(direction INPUT)
)
(port I1
(direction INPUT)
)
(port I2
(direction INPUT)
)
(port O
(direction OUTPUT)
)
(property TYPE (string "LUT3") (owner "Xilinx"))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "FE") (owner "Xilinx"))
)
)
)
Similarly, port I0, port I1 and port I2 are input ports to the LUT3 and port O is the output of
LUT3.
(instance out21
(viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "8") (owner "Xilinx"))
)
(instance out31
(viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "FE") (owner "Xilinx"))
)
Here, instance out21 is LUT2 and INIT which we get from truth-table of LUT is “8”.
Again, instance out31 is LUT3 and INIT is “FE”.
(instance (rename mux_carry_mux_out1 "mux_carry/mux_out1")
(viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "5440") (owner "Xilinx"))
)
Here, instance mux_carry_mux_out1has been renamed to"mux_carry/mux_out1". The Cell Type of
this instance is LUT4 and INIT string is “5440”.
(instance (rename mux_sum_mux_out1 "mux_sum/mux_out1")
(viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
(property XSTLIB (boolean (true)) (owner "Xilinx"))
(property INIT (string "4114") (owner "Xilinx"))
Similarly, instance mux_carry_mux_out1has been renamed to "mux_sum/mux_out1". The Cell Type
of this instance is LUT4 and INIT string is “4110”.
(net X
(joined
(portRef X)
(portRef I (instanceRef X_IBUF_renamed_1))
)
)
Input X is joined to input I of instance X_IBUF_renamed_1.
net X_IBUF
(joined
(portRef I1 (instanceRef out21))
(portRef I1 (instanceRef out31))
(portRef I3 (instanceRef mux_carry_mux_out1))
(portRef I3 (instanceRef mux_sum_mux_out1))
(portRef O (instanceRef X_IBUF_renamed_1))
Here, output of Buffer X_IBUF port O is joined to port I1 of instance out21. It is also joined to
port I1 of instance out31, port I3 of instance mux_carry_mux_out1, and port I3 of instance
mux_sum_mux_out1.
(net Y_IBUF
(joined
(portRef I0 (instanceRef out21))
(portRef I0 (instanceRef out31))
(portRef I1 (instanceRef mux_carry_mux_out1))
(portRef I1 (instanceRef mux_sum_mux_out1))
(portRef O (instanceRef Y_IBUF_renamed_2))
)
)
Here, output of Buffer Y_IBUF port O is joined to port I1 of instance out21. It is also joined to
port I1 of instance out31, port I1 of instance mux_carry_mux_out1, and port I1 of instance
mux_sum_mux_out1.
Edif file contains many things which are not required. So, to extract the required information we
run the file through a program written using Java language.
We have to extract the instance name, cell type and INIT string. And also the information
regarding the LUTs interlinked/inter-connection.
We have developed a tool using Edif Parser.
EXTRACTED DATA FROM EDIF FILE:
#LUTSTART
out21 LUT2 8
#LUTEND
#LUTSTART
out31 LUT3 FE
#LUTEND
#LUTSTART
mux_carry-mux_out1 LUT4 5440
#LUTEND
#LUTSTART
mux_sum-mux_out1 LUT4 4114
#LUTEND
The above file is processed through our software to generate the required Gate-Level
information. The Gate-Level Information is stored in files with “pla” format.
The steps are to generate pla file is shown below:
1. Open command prompt
2. Run the tool with EDIF file name as argument
3. PLA files will be created inside “output” sub-directory of the current path
FIGURE 16: SCREENSHOT 1
FIGURE 17: SCREENSHOT 2
OUTPUT PLA FILE:
#.model out21
#.model mux_carry-mux_out1
.i 2
.i 4
.o 1
.o 1
.ilb I0 I1
.ilb I0 I1 I2 I3
.ob O0
.ob O0
.p 4
.p 1
0111 1
11 1
1011 1
.e
#.model out31
#.model mux_sum-mux_out1
.i 3
.i 4
.o 1
.o 1
.ilb I0 I1 I2
.ilb I0 I1 I2 I3
.ob O0
.ob O0
.p 7
001 1
.p 4
0011 1
0101 1
010 1
1001 1
011 1
1111 1
100 1
.e
101 1
110 1
111 1
.e
BLIF –Berkeley Logic Interchange Format
Specifying the Model:
The goal of BLIF is to describe a logic-level hierarchical circuit in textual form.
Every BLIF file begins with the model declaration section. This model description is used
to refer to the current circuit in other BLIF files.
A model is a flattened hierarchical circuit. A blif file can contain many models and
references to models described in other blif files. A model is declared as follows:
.model <decl-model-name>
.inputs <decl-input-list>
.outputs <decl-output-list>
.clock <decl-clock-list>
<command>
.
.
<command>
.end
For the same circuit, as described in Fig. 1 for the PLA format,
1. Note the number of inputs, it is 4. (a,b,c,d) {Specified by “.inputs”}
2. Note the number of outputs, it is 2. (f, f1) {Specified by “.outputs”}
So, in the Blif file, we write:
.model example
.inputs a,b,c,d
.outputs f,f1
Naming the inputs and outputs
3. We define the names of the wires in the input.
For the above circuit it is a, b, c, d
4. We define the names of wires in the output.
For the above circuit it is f, f1
5. In the blif format we can specify each gate in the network by using the command
“.names”.
For example, the gate 1 in the above circuit is written as
.names a b p
11 1
What does this mean? The output p is high when the inputs a,b are both high.
In fact, this represents an AND gate in the circuit. Similarly for Gate 2 in the
above circuit, we write
.names c d q
11 1
The output p is high when the inputs c,d are both high. This represents an AND gate in the
circuit as well. The advantage is that for very large circuits specifying the truth table is very
difficult. Imagine specifying the truth table for circuit of 128 inputs and 5 outputs. Under
such cases using blif format would be easier. Blif formats also support sequential elements
like latches.
.model example
.inputs a,b,c,d
.outputs f,f1
.names a b p
11 1
.names c d q
11 1
.names p q f
1- 1
-11
.names p q f1
11
6.The end of the file is specified using the notation “.end”.
.model example
.inputs a,b,c,d
.outputs f,f1
.names a b p
11 1
.names c d q
11 1
.names p q f
1– 1
-11
.names p q f1
11 1
.end
The LUT information we have is fetch into a program which intern calls another program and
produce the following output in the form of BLIF file:
.model out21
.inputs I0 I1
.outputs O0
.default_input_arrival 0 0
.names I0 I1 O0
11 1
.end
.model out31
.inputs I0 I1 I2
.outputs O0
.default_input_arrival 0 0
.names I0 I1 I2 O0
001 1
010 1
011 1
100 1
101 1
110 1
111 1
.end
.model mux_carry-mux_out1
.inputs I0 I1 I2 I3
.outputs O0
.default_input_arrival 0 0
.names I0 I1 I2 I3 O0
0110 1
1010 1
1100 1
1110 1
.end
.model mux_sum-mux_out1
.inputs I0 I1 I2 I3
.outputs O0
.default_input_arrival 0 0
.names I0 I1 I2 I3 O0
0010 1
0100 1
1000 1
1110 1
.end

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