EE588 Digital VLSI Design Sequential Circuit Design (1) Sequencing element design Sequencing : Max/Min delay Hung-Wen Lin [email protected] YuanZe University Department of Electrical Engineering 2 Sequencing Elements Latch: Level sensitive Flip-flop: edge triggered Timing Diagrams – Sample : transparent 透明的 – Latch : Opaque 不透明的 – Edge-trigger clk D Latch clk Q D D Flop clk Q (latch) Q Q (flop) 9.2 3 Latch Design (1) Pass Transistor Latch (Dynamic) O Smallest size O Lowest clock load , High speed D VH = VDD−VTH X VTH drop X nonrestoring X back driving (輸出直接影響輸入) X output noise sensitivity floating X diffusion input (low input noise margin) Transmission gate (Dynamic) O No VTH drop D X Requires φ X 若雜訊干擾,使輸入0準位低於−VTH, 則N發生導通, 或輸入1準位高於VTH, 則P發生導通 9.3.1 φ Q φ Q φ 4 Latch Design (2) Inverting buffer (dynamic) O Restoring O No backdriving (輸出不影響輸入) D O Fixes either – Output noise sensitivity – Or diffusion input X Inverted output D 9.3.1 X Q Q 5 Latch Design (3) Tristate feedback (static) – Buffered output • No backdriving • Insensitive to output load – Buffered input • Insensitive to input noise O Robust X Rather large X Rather slow (1.5 – 2 FO4 delays) X High clock loading 9.3.1 φ X D 回授INV用弱P,上拉 部分不封 1. 省ck loading 2.減少內部寄生電容 Q φ Charge sharing 6 Flip-Flop Design Sense Dynamic Master M:Hold S:Sense Hold Sense Hold Hold Sense Hold Sense Slave M:Sense S:Hold M:Hold S:Sense M:Sense S:Hold M:Hold S:Sense M:Sense S:Hold M:Hold S:Sense M:Sense S:Hold φ φ d1 d2 X d4 d3 D d1 d2 d4 d2 Q d1 d2 d3 d4 9.3.2 φ φM hold hold φM hold hold φS hold hold φS hold hold Hold Sense Hold Sense Hold Hold Hold Hold Sense Hold Sense Hold Hold Hold Hold Hold φ P1 P2 Sense Hold Sense Hold 7 8 Pulsed generator (1) en en φ φ φp φp φ P1 P2 φp N1 en N2 en N1先開 , N2後關 P1先關 , P2後開 φp Step1 φ = 0 , a強迫拉到1 , b = 1 , φp = 0 確保 en 在 φ=0 才能送進來 Step2 φ = 0 1 (此時a = 1) , b = 1 0 , φp = 0 1 Step3 a = 1 en φ φ 0 , b = 0 1 , φp = 1 0 a b φp a Step1 把clock buffer與delay logic 整合再一起 b φP Step2 Step3 Step1 Step2 Step3 9 Pulsed latch di c φ φ φd φ N1 φd N2 c φ =0 或 φ =1 , c 都固定為1 , 上拉都鎖死 φ =0 , N1 關 ,下拉鎖死 φ =0 或 φ =1, φ =1 , φd = 0 , N2 關 , 下拉鎖死 下拉都鎖死 φ φd di c Q φ 產生正緣瞬間 , 若 di = 1 , c 產生負脈衝 , Q 被拉到1 若 di = 0 , c 沒有負脈衝 , Q 維持 0 沒有 φ 正緣 , Q 為浮接 10 Set / Reset 9.3.4 Force output low when reset asserted Synchronous vs. asynchronous set / reset 11 Enable 9.3.5 Enable: ignore clock when en = 0 , reduce power – Mux: increase latch D-Q delay – Clock Gating: increase clk-Q delay Symbol Multiplexer Design D D Clock Gating Design en 1 Q Q 0 D Q en en en D 1 Q D Q 0 D en en Q 12 Incorporating logic into latches • Highly reduce sequencing overhead • Need deal with clock skew carefully A B C D E Combinational Logic f = AB + CDE S0 φ φ D0 D1 Latch S1 Latch 13 Klass Semidynamic flip-flop x q φ = 0 , x = 1 (Pre-charge) , φd di 9.3.7 NAND如同inv , q hold (floating) 脈衝時間發 脈衝 φ = 0 1 (sense) , di 在脈衝 φ φ × φd 產生脈衝 Evaluate φ φd di x q Precharge Evaluate Precharge Evaluate Precharge Evaluate Precharge 生時進行evaluate , 並將結果傳到 x , 第二級的inv再傳遞 x , 蓋過 q Evaluate 14 Differential flip-flop φ = 0 , 斷放電路徑 9.3.8 positive feedback 中 N 失效 強制 x = xb = 1 , 即 pre-charge positive feedback 中 P 失效 類似 hold 因 x = xb = 1 , q 與 q 為 No change 此外, 因 x = xb = 1, Weak N 會自動失效 φ = 1 , positive feedback 進行 Latch Weak N 可確保低準位值不會掉到 0 , 以避免 下方差動對 與 電流源 進入 triode region Positive feedback P P N N Analog input φ xb x φ=1 Sense φ=0 Pre-charge q qb x 0 1 1 0 xb 1 0 1 0 不會出現 的情形 q qb 1 0 0 1 No change 1 1 15 Dual edge-triggered flip-flop φ=1 φ sample φ=0 hold hold P1 N1 sample hold的準位為全幅, 因此P1或 N1其中一個關掉, 無直流路徑, 不影響左邊sample的直流準位 16 True Single Phase Clock flip-flop (1) [1] [2] [3] CK CK Q CK CK Q CK Q D CK D CK D CK [1] J. Yuan and C. Svensson, ”High speed CMOS technique.” JSSC 1989. [2] B. Chang, et al.” A 1.2GHz CMOS Dual Modulus Prescaler Using New Dynamic D-Type Flip Flop.” JSSC, 1996. [3] C.-Y. Yang, et al. ” New Dynamic Flip-Flop for High-Speed Dual-Modulus Prescaler.” JSSC, 1998 17 True Single Phase Clock flip-flop (2) Ck = 1 ( with D transition) ck M2 rst M7 ck ck M6 M4 M1 M3 ck 0 1 D M5 1 0 0 D 1 M2 1 0.5 M1 rst M7 ck M6 M4 0.5 0.5 qb 0.5 0.5 0.3 0.3 0 0 0 0 M1 M3 ck M5 Ck = 1 (without D transition) Ck = 0 ck rst 1 0 qb D M2 M7 ck ck M6 M4 1 qb 1 0.5 0.8 M3 ck M5 M2 1 0 0 D 1 M1 rst M7 ck M6 M4 0.5 0.3 0 0.5 M3 ck M5 qb 18 Sequencing 9.1 Combinational logic – Output depends on current inputs Sequential logic – Output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline in CL Finite State Machine out 19 Sequencing Overhead If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay – Called sequencing overhead / clocking overhead – Inevitable side effect of maintaining sequence 20 Sequencing methods (1) Flop Flop Flip Flops 2-phase transparent latches 1/3通 資料從輸入到A 資料從B到C 1~3都鎖 所 有資料都停住 1~3都鎖 所 有資料都停住 2鎖 1/3鎖 2通 資料從A到B A 1 B 2 C 3 9.2.1 21 Sequencing methods (2) Pulsed latch Latch1 放資料進來 先前在combinational logic處理的資 料從Latch2出去 tpw p p 資料進來後, Latch1關掉 ,資料在combination logic處理, 經一段時間後傳到latch2輸入 Combinational Logic p 22 Timing diagrams 9.2.1 tpd A A 最小與最大延遲 tpd tcd Combinational Logic Y tcd Y Propagation delay Contamination delay clk clk tsetup thold DFF取樣 tsetup thold 取樣前多久輸入要準備好 D Q D tpcq 取樣後要輸入要持續多久 Q tccq Latch 進入hold前後 tpcq tccq clk Q propagation delay tpcq clk Q contamination delay Latch 進入sense前後 tpdq tcdq clk clk D Q D tccq tcdq D Q propagation delay D Q contamination delay thold tsetup Q tpdq 23 Max-delay: flip-flops 9.2.2 t pcq + t pd + tsetup ≤ Tc t pd ≤ Tc − ( tsetup + t pcq ) 14243 sequencing overhead clk Q1 Combinational Logic clk D2 Tc clk Q1 D2 tpcq tpd tsetup 24 Min-delay: flip-flops 9.2.3 thold : clk正緣後, F2輸入需維持多久,才能被F2吃進去 tccq + tcd : clk正緣後, F2的輸入經多久會被F1的輸出覆蓋 資料在F2的輸入被F2吃進去前,這資料不能被F1輸出所覆蓋 後發生,時間延遲較長 clk Q1 clk thold Q1 tccq D2 clk tcd tcd CL D2 先發生,時間延遲較短 tcd + tccq ≥ thold tcd ≥ thold − tccq 25 L2 L1 Max delay: pulsed latches t pd ≤ Tc − t pdq 門先開 (φP↑), 資料直接通過 Tpw > Tsetup (類似2-phase latch) 資料等, 開門(φP↑) 後才能通過 Tpw < Tsetup t pcq + t pd + tsetup − t pw ≤ Tc ⇒ t pd ≤ Tc − t pcq − tsetup + t pw 26 Min-delay: pulsed latches φp負緣需先使L2吃進D2,接著φp正緣使L1產生Q1才能經過CL蓋過D2 後發生, 時間延遲較長 先發生, 時間延遲較短 tcd + tccq ≥ thold + t pw tcd ≥ thold − tccq + t pw p tccq thold Q1 D2 tcd L2 tpw L1 tccq tcd Max delay: 2-phase latches t pdq + t pd 1 + t pdq + t pd 2 ≤ Tc ⇒ t pd = t pd 1 + t pd 2 ≤ Tc − 2t pdq tpd1 1 D1 tpd2 2 1 Q1 Combinational D2 Q2 Combinational D3 Logic 1 Logic 2 tpdq tpdq 1 2 門先開 (φ φ1↑) , D1資料直接通過 D1 Tc tpdq tpd1 Q1 D2 門先開 (φ φ2↑) , D2資料直接通過 tpdq tpd2 Q2 D3 Q3 27 28 Min-delay: 2-phase latches 後發生,時間延遲較長 1 2 tcd Q1 CL D2 先發生,時間延遲較短 tnonoverlap + tccq + tcd ≥ thold tcd ≥ thold − tccq − tnonoverlap
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