Wide-Bandwidth Interface Circuit Design Clock and data recovery Hung-Wen Lin [email protected] YuanZe University Department of Electrical Engineering Clock and Data Recovery (CDR) Noisy data Clean data Decision circuit D Q CDR Optimum sampling Threshold of Decision circuit Din CKout t General considerations ‧CDR must output a frequency (CKOUT) equal to the data rate ‧CDR must generate a certain phase relationship with respect to data allowing optimum sampling (usually the midpoint) of the bits by the clock ‧CDR must exhibits small jitter to reduce the jitter of retimed data WBIC Clock and Data Recovery 2 Clock and data recovery architecture PLL-based data recovery VCO Up Din PD CP LPF Dn Dout Oversampling-based data recovery PLL Din WBIC OverSampler Optimum phase Dout Clock and Data Recovery 3 Edge detection for data (1) Differentiation d (...) dt H (s) = s 怎麼對資料作微分? dDIN D (t ) − DIN (t2 ) DIN (t1 ) − DIN (t2 ) ⇒ IN 1 = dt t1 − t2 ∆t Circuit implementation example Din Din Δt A Vout Δt A Din Din A Vout Din Δt Vout Δt A Vout Din Din A A Vout Δt Vout Δt WBIC Clock and Data Recovery 4 Edge detection for data (2) XOR XOR DIN VO Δt A Ab Ab A B Bb B Bb DIN’ VO DIN DIN ∆t ∆t DIN’ XOR A Ab DIN’ B WBIC XOR Clock and Data Recovery Bb 5 Edge detection for data (3) ‧Delay time of XOR is critical DIN VO Δt DIN DIN’ DIN’ ‧Delay circuit : level shifters VO t Short delay time VO DIN DIN ∆t ∆t DIN’ DIN’ DIN DIN’ VO t Long delay time WBIC Clock and Data Recovery 6 Edge detection for data (4) I1+I2 VO VI ID1 VIB I1 VA ID1 VB M1 A I1 B CD I2 s rO CD A CD B = rO 1 + s rO CD Source coupled pair with capacitive degeneration Each rising edge at the gate of M1 momentarily turns M2 off, allowing both I1 and I2 to flow through M1 , VB then falls at a rate of I2 /CD until M2 turns on WBIC Clock and Data Recovery 7 Edge detection for clock (1) CK 1 CK 2 VPD (t ) = sin(ωC t + θ 1 ) × sin(ωC t + θ 2 ) = sin(2ωC t + θ 1 + θ 2 ) + sin(θ 1 − θ 2 ) VPD ∫ (t ) = nTCK 0 VPD (t ) dt nTCK 可偵測相位誤差,輸出平均 值與相位差呈線性關係 = sin(θ 1 − θ 2 ) = sin ∆θ ∝ ∆θ 只在小信號 底下成立 io = g m v in VO io = g m v in1 v in 2 vin vin2 vin vin vin 2 WBIC Clock and Data Recovery 8 Edge detection for clock (2) CK 1 CK 2 V PD (t ) ∆φ ≈ 0 V PD (t ) ∆φ ≈ π / 2 CK1 CK2 V PD (t ) −π 0 ∆φ = φ 1 − φ 2 ∆φ ≈ π π ∆φ ≈ −π / 2 CK1 CK2 V PD (t ) WBIC Clock and Data Recovery 9 Edge detection for clock (3) Re cov ery clock Random data CK 1 CK 2 DIN CK V PD (t ) VOUT (t ) = ∑ an sin(ω D ,n t + θ D ) × sin(ω CK t + θ CK ) ≠0 sin[(ω D ,n + ω CK ) t + (θ D ,n + θ CK )] = ∑ an + sin[( ω − ω ) t + ( θ − θ )] D , n CK D , n CK VOUT ≠0 VOUT Data lags clock ∫ (t ) = N TB 0 VOUT (t ) dt N TB 無法偵測資料與時脈 的相位誤差 Data leads clock DIN DIN CK CK VOUT VOUT WBIC ≈0 Clock and Data Recovery 10 DFF Phase detector (1) ‧Data samples clock - DIN and CK are swapped, each rising edge of DIN samples CK - If DIN lags CK,DFF outputs a positive pulse - If DIN leads CK,DFF outputs a negative pulse VOUT Bang-bang PD CK D Q VOUT Δφ’ = φD – φCK VOUT DIN Δφ = φCK – φD CK CK DIN DIN VOUT VOUT WBIC Clock and Data Recovery 相位誤差與輸出值 為非線性曲線! 11 DFF Phase detector (2) Half-wave rectification CK D Q VOUT CK DIN DIN dDIN dt H Full-wave rectification D Q CK DIN CK VOUT DIN dDIN dt DIN D Q WBIC Clock and Data Recovery 12 CDR circuit using DFF PD Decision circuit D Q At lock condition DIN CKO CDR D Q DIN WBIC DO LPF VCO CKO D Q DO Clock and Data Recovery 13 Nonidealities of CDR (1) Feedthrough path1 LPF D Q • Data-to-VCO feed-through should be avoided CKOUT VCO Feedthrough path2 DIN D M1 WBIC M2 DOUT Decision circuit M 1 Din Feedthrough path1 Din Phase detector Q M3 Clock and Data Recovery M2 Feedthrough path2 M3 14 Nonidealities of CDR (2) D Q ∆t DIN LPF CKO VCO ∆t CKO’ D Q Data-Q Q DOUT Optimum sampling Actual sampling CK-Q DIN CKO ∆t are caused by difference between CK-to-Q and Data-to-Q WBIC Clock and Data Recovery 15 Phase detector for random data (1) DIN DIN VO Δt A A VO Δt • Edge detection : a pulse for each data transition. DIN VO DIN CK B CK DO B VO • Linearly phase difference : VO contains pulses whose width varies linearly with the phase difference between DIN and CK Average of VO is linearly proportion to the phase difference ‧Data is retimed inside PD DO WBIC Clock and Data Recovery 16 Phase detector for random data (2) • However, Average of VO is a function of data transition density Different phase errors may result in the same DC output Higher phase error Lower transition density DIN B CK Lower phase error Higher transition density VO DIN DIN DO CK B VO CK B VO • To overcome the above ambiguity, the proportional pulse is accompanied by reference pulses (next page), which appear on data edges but exhibit a constant width to eliminate the pattern dependency (Transition density) Hogge PD WBIC Clock and Data Recovery 17 Hogge PD (1) Y IP VO B X DIN D Q D Q • ∆Y : difference between transition of DIN and rising of CK • ∆X : constant difference of TCK /2 • Linear PD A IP CK 鎖定時, ∆Y佔1/2資料週期,CK 上升緣直接取樣資料中心 DIN DIN CK CK B B A A Y X VO WBIC ∆Y Y ∆X X No data transition ∝(∆Y – ∆X) VO Clock and Data Recovery ∆Y ∆X No data transition 18 Hogge PD (2) DIN Y IP VOUT B X DIN D Q CK D Q CK B A ∆Y Y A IP ∆X X VOUT Ripple I P TCK ⋅ CP 2 • At lock condition ∆Y = TCK / 2 , ( ∆Y – ∆X ) = 0 Falling edge of CK is adjusted to align transition edge of DIN TCK /2 skew between X and Y causes a triangular ripple at VOUT for each data transition noise of VCO (key drawback of hogge PD) WBIC Clock and Data Recovery 19 Nonidealities of Hogge PD (1) Din Δt Y B FF1 DIN CK D Q D X Q A CK B Y ∆φ ∆t ∆φ ∆t ‧Due to CK-to-Q delay of FF1, B is delayed by ∆t, yielding a wider pulse at Y than the phase difference (∆φ ) between DIN and CK ‧Reference pulse at X remains the same TCK /2 At steady state, DIN and CK sustain a skew of ∆t WBIC Clock and Data Recovery 20 Nonidealities of Hogge PD (2) ‧Insert a DFF-like delay cell (Δt =CK-to-Q) VOUT Δt Y B DIN DIN D Q DIN D Q X A CK DIN ‧Widen the reference pulse by ∆t Inserting a delay stage at A CK B B Y A A’ Match DIN DQ DQ Δt A’ A Y X CK X WBIC Clock and Data Recovery 21 Modified Hogge PD CK DIN D Q DIN’ V1 D Q V2 D Q D Q V3 V4 Charge pump Original Hogge PD (+A) VCP –A DIN CK D1 D2 D3 D4 V1 V2 V3 V4 VCP +A –A +A –A ‧Additional XOR and Latch create negative triangular pulse ( –A ) offset by TCK and with respect to the original pulse Produce a zero offset at VCP VCO phase is lowered WBIC Clock and Data Recovery 22 CDR using Hoggle PD Din IP Y CK B Din FF FF D Q D Q X A IP VCO Vout B RP CP C2 Y A X - Under locked condition, X and Y both contain a pulse width of TCK /2 - Require a very board bandwidth at X and Y to ensure complete switching of the charge pump and avoid a dead zone. WBIC Clock and Data Recovery 23 Alexander Phase Detector (APD) Data transition occurs in negative half period (180° ~0°) Data transition occurs in positive half period (0° ~180°) DIN DIN CK CK 180° 0° 180° 0° 180° 0° DIN D Q Q1 Q2 CK FF WBIC Q3 D Q Latch 180° 0° 180° φCK – φD = ∆φ < 0 CK Lead DIN DIN D Q 0° CK Lag DIN FF D Q 180° Falling edge of clock ( φCK ) lags transition edge of data ( φD ) Rising edge of clock ( φCK ) leads transition edge of data ( φD ) Falling edge of clock ( φCK ) leads transition edge of data ( φD ) Rising edge of clock ( φCK ) lags transition edge of data ( φD ) φCK – φD = ∆φ > 0 FF 0° 180° Q4 Q3 Q1 Q1 Q2 Q3 CK Clock and∆φ Data > 0 Recovery , CK Lag DIN DIN Q2 CK ∆φ < 0 , CK Lead DIN 24 Timing diagram of APD DIN FF D Q CK D Q FF Lag FF Q1 Q3 D Q D Q L Q2 Q4 Lead DIN 1 2 2 DIN 1 5 3 4 5 CK CK 1 Q2 Q3 ∆φ φCK – φD = ∆φ > 0 3 4 Q1 Lead – Lag φCK – φD = ∆φ < 0 Q4 3 5 Q1 1 3 Q2 2 3 5 1 3 2 4 Q3 4 2 1 4 Q4 Lead Lead Lag Lag ‧APD is a bang-bang system, exhibiting a high gain in the vicinity of ∆φ =0 ‧APD provides inherent data retiming WBIC Clock and Data Recovery 25 APD V.S. DFF PD CK D Q DIN CK VOUT DIN FF D Q CK Lag FF Q1 D Q Q2 Lead 3 4 D Q FF Q3 D Q L Q4 DIN 1 2 CK DIN Q1 VOUT Q2 Q3 • APD is better than DFF PD - W/o data transition, APD outputs a zero DC less ripple in VCO control. - Inherent data retiming • Gain of APD is a function of data transition density WBIC Clock and Data Recovery 5 Q4 1 3 5 1 3 2 4 2 4 Lead Lag 26 APD implementation Din D Q D Q Q1 CK D Q FF Lag FF FF Q3 Lead Q2 D Q L Q4 D Latch XOR Q D CK WBIC VOUT A A B Clock and Data Recovery B 27 CDR using APD • Compare to Hogge PD (Linear PD), APD (Bang-bang PD) don’t use narrow pulse and high speed switches to drive CP V/I has a lower BW requirement ‧As CDR is locked… - XOR experiences metastable level at Q3 and Q4 at most of the time - Falling edge of CK is aligned to transition edge of DIN - Produce a valid data waveform at Q1 and Q2 DIN DIN CK CK DQ DQ Q3 DQ V/I VCO LP Q2 DO1 Q4 DO2 L Lag DIN WBIC DQ FF lock CK Q1 Lead V/I (Lead – Lag) in current domain Clock and Data Recovery 28 CK頻率 = 0.5 X 資料速率 ex.0.5HGz 1Gbps Half-rate PD (1) ‧CDR may sense full-rate random data but employ a half-rate VCO ‧Relax the BW requirements of VCO and DFF ‧Data transitions may be detected if both edges of the half-rate clock are utilized to sample the input data, here duty cycle distortion of clock is a key issue Latch1 DIN DQ A ∆φ CK DQ B Sense Hold Sense Hold Sense Hold Latch2 1. 一邊固定為初值, 另一邊則允許輸入 何時輸入改變, 會直接傳遞至XOR輸出 2. DFF1 hold /DFF2 sense 偵測CK負半週是否發生資料轉態 DFF1 sense /DFF2 hold 偵測CK正半週是否發生資料轉態 3.系統最終會鎖定在∆φ全為1或全為0的狀態 WBIC Hold Sense Hold Sense Hold Sense ∆φ Clock and Data Recovery 29 Half-rate PD (2) L1 DIN DQ VOUT A CK VOUT DQ B TB 0 2 T T ∆φ ≈ ± B or CK 2 4 − L2 ∆φ ≈ 0 , ∆φ > 0 TB 2 ∆φ = φCK − φD ∆φ ≈ 0 , ∆φ < 0 DIN DIN DIN CK CK CK 實線sense A 虛線hold B A A B B VOUT VOUT VOUT WBIC Clock and Data Recovery 30 Linear Half-rate PD L1 D Q DIN L3 A D Q C Do1 CK B D D Q D Q L2 L4 Vout If DIN has a transition, C⊕ ⊕D generate a pulse width of TCK /2 DIN CK Do2 C D C D 假如AB發生轉態,那CD會產生一 個週期的”−1” VOUT Vref TCK 2 DIN VOUT TCK 4 CK −π A C B D 0 π − π π 2 0 2 • If CK edge is to strobe the data in the middle of the eye, then A⊕B is TCK /4 A⊕B o1 C⊕D WBIC o2 o3 o4 r1 r2 r3 o5 r4 • C⊕D needs to be halved to equal TCK /4 r5 • Half-rate PD retimes & DeMUX DIN Clock and Data Recovery 31 Half-Rate Early-Late PDs DIN DQ A X (Lead) .A /B /C without retiming latch Metastable Skew (A-B, C, Lead-Lag) Y (Lag) CKI CKI DQ CKQ DQ C CKQ B DIN retime CKI A CKQ B DIN A B C A B C C metastable CK取樣轉態 中的資料 A⊕B • Like APD, it’s a bang-bang PD • CKI is used to track the edge of data eye B ⊕C • CKQ is used to sample the middle of data eye •.A /B /C need additional retiming latches before they applied to XOR WBIC Clock and Data Recovery 32 Frequency detector for random data ‧FD generate an output whose average represents the polarity and the magnitude of frequency difference. Mixing and Differentiation for Frequency Detection x1 (t ) = A1 cos ω1t x2 (t ) = A2 cos ω2 t LPF d(...) dt XO(t) A1 A2 [cos(ω1 + ω2 )t + cos(ω1 − ω2 )t ] 2 A1 A2 A1 A2 (ω1 − ω2 ) × sin(ω1 − ω2 )t X O (t ) = cos(ω1 − ω2 )t ' = − 2 2 x1 (t ) x2 (t ) = ∆ω is AM-modulated in XO(t) X O (t ) = 0 WBIC fails to detect the frequency difference Clock and Data Recovery 33 Quadricorrelator as a frequency detector (1) Periodic CK2 X2, I 比較兩個clock X1(t) Periodic CK1 LPF XA X2, Q LPF d(...) dt XB X A (t ) = A1 cos ω1t × A2 cos ω2 t = XC LPF XO(t) A1 A2 cos (ω1 + ω2 ) t + cos (ω1 − ω2 ) t 2 dX A (t ) A1 A2 =− (ω1 − ω2 ) × sin (ω1 − ω2 ) t dt 2 A1 A2 X B (t ) = A1 cos ω1t × − A2 sin ω2 t = sin (ω1 + ω2 ) t − sin (ω1 − ω2 ) t 2 2 dX A (t ) A1 A2 X C (t ) = X B (t ) = − (ω1 − ω2 ) sin (ω1 − ω2 ) t sin (ω1 − ω2 ) t dt 2 WBIC Clock and Data Recovery 34 Quadricorrelator as a frequency detector (2) Periodic CK2 X2, I LPF X1(t) Periodic CK1 XA X2, Q LPF d(...) dt XB XC LPF XO(t) 2 2 AA Last page⇒ X C (t ) = − 1 2 (ω1 − ω2 ) sin (ω1 − ω2 ) t 2 2 AA = 1 2 (ω1 − ω2 ) cos 2 (ω1 − ω2 ) t − 1 2 2 AA ⇒ X O (t ) = 1 2 (ω1 − ω2 ) 2 WBIC 當CK1與CK2的頻率接近時,我們需要 非常低截止頻慮(高成本)的濾波器 Clock and Data Recovery 35 Quadricorrelator as a frequency detector (3) Periodic CK 2 CKI LPF Periodic CK1 X1(t) XA d(...) dt XC CKQ LPF XB XO (t) d(...) dt ω1 − ω2 X A = A1 cos ω1t × A2 cos ω2 t = A1 A2 cos (ω + ω ) t + cos ∆ω t ⇒ dX A = − A1 A2 ∆ω × sin ∆ω t 1 2 2 dt 2 X B = A1 cos ω1t × − A2 sin ω2 t = A1 A2 [sin(ω + ω ) t − sin ∆ωt ] ⇒ dX B = A1 A2 ∆ω × cos∆ωt 1 2 2 dt 2 2 2 dX A dX B A A A1 A2 XO = XB + XA = ∆ω sin 2 ∆ω t + cos 2 ∆ω t = 1 2 ∆ω dt dt 2 2 ( ) 輸出端可省去低通濾波器 WBIC Clock and Data Recovery D 36 Frequency Detector (1) Under-sample fCK2 < fCK1 CK1 XA DQ 180° 對ck2來說,ck1 一直往前走 0° CK2 / CK3 fCK3 > fCK1 對ck3來說,ck1 一直往後走 Over-sample 0 1 2 3 4 5 6 7 8 9 10 11 .9 .0 CK1 .0 .1 .2 .3 .4 .5 .6 .7 .8 CK2 .0 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 CK3 WBIC CK1 1 2 3 4 5 6 7 8 CK2 = 1.1×CK1 1.1 2.2 3.3 4.4 5.5 6.6 7.7 8.8 9.9 11.0 12.1 CK3 = 0.9 × CK1 0.9 1.8 2.7 3.6 4.5 5.4 6.3 7.2 8.1 Clock and Data Recovery 9 10 9.0 11 9.9 37 Frequency Detector (2) DQ CKI fCK < fD XA 取樣的速度比較快,會感覺被取樣的往後退 CKI DIN CKQ Δt CKQ DQ XB DIN XA CK Q XA : 0 XB : 1 XA : 1 XB : 1 fCK > fD XB 4 3 fCK > fD 2 1 4 取樣的速度比較慢,會感覺被取樣的往前走 CKI 2 1 CK I 3 4 f <f CKQ CK D CK I XA : 0 XB : 0 XA : 1 XB : 0 CK Q WBIC DIN XA 4 2 1 XB Clock and Data Recovery 38 Frequency Detector (3) 3 2 1 4 3 2 1 4 CK Q XA : 0 XB : 1 XA XA : 1 XB : 1 fCK > fD 2 1 CK I 4 3 fCK < fD CK I XA : 0 XB : 0 XA : 1 XB : 0 fCK < fD XA lag XB 取樣到0代表參考時脈頻率 太低,要加速 XB 3 4 1 2 3 4 1 2 XA fCK > fD XA lead XB XB DIN CKQ XB D Q CK Q CKI VO XA D Q D Q VO fCK – fD • Rising edge of XB(t) are used to sample XA(t) -VO is high for fCK > fD , VO is low for fCK < fD • Overall FD exhibits a bang-bang characteristic WBIC Clock and Data Recovery 39 Frequency Detector (4) • If fCK – fD is too large ( > fCK /4 ), FD will fail to lock. XA : 0 XB : 1 CK Q 2 1 3 4 CK I XA : 0 XB : 0 ( fCK CK Q WBIC Nonideal f CK 2 CK I VOUT f CK 4 fCK – fD XA : 1 XB : 0 1.2 − fD ) ≈ fCK 4 2 1 3 4 Ideal VOUT XA : 1 XB : 1 ( fCK − fD ) ≈ 2 fCK 4 2 1 3 4 Clock and Data Recovery ( fCK fCK – fD f CK 4 f CK 2 − fD ) ≈ 3 fCK 4 2 1 3 4 40 Full-rate referenceless CDR DOUT DOUT PD DIN LPF1 PD DIN Loop2 : PLL VCO CKQ CKI FD D Q D Q D Q Course VCO LPF Loop1 : FLL CKQ CKI FD Fine D Q D Q D Q LPF2 ‧FD produces a DC level that drives VCO frequency toward data rate ‧When fCK – fD falls within the capture range of Loop2, PD takes over • Loop1 and Loop2 may interact heavily that CDR fails to phase-lock Improved by decomposing VCO control into coarse (Narrow BW, LPF1) LPF1 and fine (Wide BW LPF2) LPF2 inputs • Short-term spectral lines close but unequal to data rate may confuse FD • In phase-locked state, bang-bang FD still produce extraneous pulses BW of FLL is typically much smaller than of PLL WBIC Clock and Data Recovery 41 CDR with coarse and fine VCO control (1) Loop 1 : PLL fCK Up DIN PD DOUT fREF PD Dn CP&LPF1 Vfine ‧VCO2 is a replica of VCO1, and is frequency locked to N× fREF which is ideally equal to input data late VCO1 Vcourse Up Dn CP&LPF2 Loop 2 : FLL 1/N ‧R/C at Vcourse reduce the noise form loop2 to loop1 VCO2 ‧Loop1 phase-locks VCO1 to DIN through Vfine ripple on Vfine induce a lower jitter at DOUT ‧ Loop1 must achieve sufficiently wide capture range to guarantee lock Inevitable random mismatches between VCO1 and VCO2 lead to a substantial center frequency mismatch Incoming data is not exactly equal to N× fREF Crystal oscillator may suffer from an error of 5~10ppm ‧VCO1 and VCO2 operate at different frequencies pull each other through VDD improved by using differential swings for both VCOs WBIC Clock and Data Recovery 42 CDR with external reference (1) 1.First enables loop2 and lock the oscillator to N× fREF 2 Disabling loop2 and enabling loop1 when ∆f = | fB – fREF | drops to a sufficiently small value (within the capture range of loop1) loop1 3.loop2 activated again if loop1 loses lock. ‧Charge injection and clock feedthrough of switches must be examined carefully ‧Charge sharing between CP1 and CP2 heavily disturbs the VCO controls ‧Compared to CDR with 2X VCOs - W/o mismatch and frequency pulling effect between VCOs - W/o course and fine controls DIN DOUT Loop 1 : PLL Up PD Dn CP1 LPF LPF fREF PFD CP2 fB VCO Loop 2 : FLL 1/N Lock detector WBIC Clock and Data Recovery 43 CDR with external reference (2) DOUT Up PD DIN Dn CP1 LPF LPF FREF PFD VCO RP CP CP2 fB C2 RP CP1 S1 C2 CP2 Lock detector 1/N • C2 in LPF attenuate the transition noise from PLL to CDR, generally C 2 < 0.2 C P • Damping factor of PLL : ς = RP 2 ‧ PLL and CDR require different ζ WBIC I P C P KVCO 2π N variable CP Clock and Data Recovery 44
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