SFP＋① LVDS/CML(with DC Biased）) LVDS/CML （with DC Biased） SFP＋② LVDS/CML（with DC Biased） LVDS/CML （with DC Biased） SDI In/Out ① SDI In/Out ② SDI In/Out ③ SDI In/Out ④ 4.7uF 3G-SDI HD/SD 4.7uF 3G-SDI HD/SD LMH0387① LMH0387② 4.7uF 3G-SDI HD/SD LMH0387③ 4.7uF 3G-SDI HD/SD LMH0387④ Board-A LVDS （with DC Biased） LVDS （with DC Biased） About detail of connection, Please refer to next page. D0 +/- B D0+/D0 +/- A D1 +/- B D1+/D1 +/- A FPGA D2 +/- B LVDS （with DC Biased） D2 +/- A D2+/- LVDS （with DC Biased） D3 +/- B D3+/D3 +/- A TS3DV642 LVDS （with DC Biased） LVDS （with DC Biased） FPGA LVDS （with DC Biased） LVDS （with DC Biased） Board-B ※1 Board-A or Board-B are connected to TSDV642. ※2 This diagram is the connecting schematic. So, actually, all of signals are differential signaling. －Detail of connection to TS3DV642－ ①Pattern1: Board-A, SFP+① and SFP+② Board-A LMH0387① LMH0387② LMH0387③ LMH0387④ LVDS （with DC Biased） LVDS （with DC Biased） LVDS （with DC Biased） LVDS （with DC Biased） LVDS/CML(with DC Biased） <TS3DV642> D0 +/-A D1 +/-A A D2 +/-A D0 +/- D3 +/-A D1 +/- D2 +/- D0 +/-B FPGA SFP＋① LVDS/CML(with DC Biased) D3 +/- D1 +/-B B SFP＋② LVDS/CML(with DC Biased) D2 +/-B LVDS/CML(with DC Biased） D3 +/-B ②Pattern2: Board-B, SFP+① and SFP+② Board-B LVDS （with DC Biased） LVDS （with DC Biased） FPGA LVDS （with DC Biased） LVDS （with DC Biased） LVDS/CML(with DC Biased） <TS3DV642> D0 +/-A D1 +/-A A D2 +/-A D0 +/- D3 +/-A D1 +/- D2 +/- D0 +/-B SFP＋① LVDS/CML(with DC Biased) D3 +/- D1 +/-B B SFP＋② LVDS/CML(with DC Biased) D2 +/-B LVDS/CML(with DC Biased） D3 +/-B FPGA
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