High Frequency Test Methods for Laminate Materials (HF) Project Project Update HDPUG Meeting Sept. 20-21, 2011 Spain OBJECTIVE Using all viable electrical test methods for speeds above 2 GHz, test wide range of high frequency (below IPC ~0.010 Df at 1 GHz) laminate materials including most commercial (volume production with UL approval) “halogen-free” laminate materials. Material resin content/construction, Cu foil surface roughness/type and moisture content shall be consistent and not variables in this Phase 1 testing. Goal Compare the results of the many various higher frequency Dk and Df test methods for each of the materials tested. • Focus on identifying possible correlations for future work • Identify test method problems and/or discrepancies in results SCHEDULE Completed selecting laminate materials to be tested and high frequency test methods to be used. Completed test board layout, fabrication and test facility commitments. Remaining schedule: 1) Complete test board construction and design data package – est. Sept. 23rd 2) Fabricators order materials – est. Sept. 30th 3) Fabricators receive materials – est. Nov. 1st 4) Manufacture of test boards completed and shipped to testers – etc. Nov. 30th 5) Testing starts – est. Jan. 1, 2012 6) Testing is completed – est. Feb. 1, 2012 7) Final report completed – est. Feb. 15, 2012 PROCESS FLOW CHART TV Design 6 Layers Fabrication: Testing: Laminate Manufacturers Viasystems Hitachi SPC-IPC Hitachi Tri-Plate Resonator JPCA TM0001 Viasystems 4-Port VNA Isola Bereskin Stripline TTM Shengyi Iteq Stripline IPC 2.5.5.11 IPC 2.5.5.5, IPC 2.5.5.12 IPC 2.5.5.13 SPDR NIST SPC Resonator Interobotics SPP EBW Intel SET2DIL Cisco S3 LAMINATE MATERIALS Not Halogen-Free Halogen-Free Matsushita Megtron-6 Hitachi FX-2 Iteq IT-150D or DA Nelco 4000-13EP SI Iteq IT-200LK Isola IS-415 Matsushita R-2125 Isola 370HR Mitsubishi MGC FL700 EMC EM-828K Iteq IT-168G Hitachi MCL HE 679G TUC TU-862HF Matsushita R-1566W Shengyi S-1165 Iteq IT-170GR or GRA Hitachi MCL-E-75G TEST METHODS Dk/Df: SPP (IBM) S-3 (CISCO) Bereskin Stripline (Isola) Split Post Dielectric Resonator Cavity (IPC 2.5.5.13) Tri-plate Line Resonator (JPCA-TM001) SET2DIL (Intel) EBW Stripline (IPC 2.5.5.5) NIST Other (for control and monitoring): DC Resistance Propagation Delay TEST BOARD LAYOUT RESOURCES/SUPPORT Reference SCHEDULE on Slide #3: • Two fabricators share building all test boards • Each laminate material will be supplied to one fabricator • Oracle to fund Interobotics for SPP testing • Hitachi to do JPCA testing • Iteq & Hitachi & Shengyi to do IPC testing • Isola to do Bereskin Stripline testing • CISCO to do S-3 testing • SET2DIL testing by Intel or TBD • Prop Delay and DC Resistance test sites TBD All other activities to be sourced through and funded by the project members. No additional HDP funding required. PARTICIPANTS Contributors, Fabricators, Testers • Karl Sauter, Oracle Corp. • Mike Freda, Oracle Corp. • Holle Galyon, Viasystems • Eric Mieglitz, Viasystems • Chris Katzko, TTM Meadville • Joe Smetana, Alcatel-Lucent • Scott Hinaga, CISCO • David Senk, CISCO • Jeff Taylor, IBM • Michael D. Janezic, NIST • Dylan Williams, NIST • James Baker Jarvis, NIST Laminate Material Suppliers: • Albert Chen, EMC • Terry Fischer, Hitachi-Chemical • David Bedner, Isola • Peg Conn, Isola • Rick Lovelady, Iteq • Robert Huang, Iteq • DeAnn Drottz, ParkElectro • Scarlet Wang, ShengyiGuangdong • Kevin Zhang, ShengyiGuangdong • Frieda Yip, Shengyi-Guangdong • CS Ng, TUC-Taiwan
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