OrCAD Sigrity ERC

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OrCAD Sigrity ERC
Josh Moore – Product Management Director
Cadence OrCAD Solutions
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Cadence Sigrity – Industry-leading SI / PI
Solution
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seof choice for power
• Product
and signal
analysis
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• Layout-based frequencydomain SI / PI simulation o
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– Integration with full wave 3D EM
solver
– Highly accurate modeling of PCB
structures
• Single-ended and mixed-mode
results and post-processing
• Unique capability for ensuring
accuracy down to DC
• Targeted workflows to
streamline setup operations
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Frequency domain SI, PI and EMC
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Different SI / PI / EMI Levels for Different Needs
G• rSimulations and analysis can be done at four levels
as
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• Both layout-based
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– Based on considerations of trace / via couplings,
non-ideal PDN, etc.
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Layout-based, Time-domain SI / PI Simulation
Gr
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se is industry’s only layout-based, time• SPEED2000™
domain SIr/ PI solution
Us SI / PI analysis from level 1 to 3
• Five workflows for
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Geometry- and Simulation-based Layout Checks
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Coupling
overlay in
layout
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Coupling plot
Electrical Rules Checks
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Coupling table
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SI Barriers for PCB Designers
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Complex Flow for Simulation and Verification
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Transistors
model
LEF/DEF
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IBIS model
Conversion with
T2B
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C
IO Model
Extraction with
XcitePI
IBIS 5.0 model
on
SPICE Netlist
BRD
MCM
GDS
RLC model
Extaction with
XtractIM
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S Parameter
Extraction with
PowerSI
SPICE Netlist
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SPICE Netlist
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• Comprehensive SI / PI simulation and analysis relies on
experienced, well trained engineers with sophisticated tools
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© 2014 Cadence Design Systems, Inc..
Common SI Analysis Needs to be Simple
Gr
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se (ringing)
• Reflections
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– Impedance mismatch
• Crosstalk
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– Electromagnetic coupling between adjacent signal lines
• Return path discontinuity
– Layer transitions or plane split crosses
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Simulation and Design Rule Check
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• Ideally,
100% driven
and validated by
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simulation U
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esimulation
• Typically, pre-layout
r
results drive design rules
Co
• Only small portion covered n
Simulations
Designs
feDesign
by simulation
Rule Check
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• PCB DRCs usually contain
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only dimension information
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such as length, width,
distance, spacing, etc.
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• What do constraints / DRCs
forget to tell you?
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© 2014 Cadence Design Systems, Inc..
DRC Correct or Electrically Correct?
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sedesign rule checks for dimension will not validate
• Simple
electrical r
characteristics
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Question:
1. Are the DRC results of these 2 structures
the same or different?
Same
2. Do these 2 structures have the same or
different electrical properties? Different
3. Do these 2 structures have the same
impedance or not?
Case 1:
Case 2:
5mil
5mil
3mil
6mil
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© 2014 Cadence Design Systems, Inc..
DRC Correct or Electrically Correct?
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se simulation, defines a trace width to be 5 mils for
• Pre-layout
a target impedance
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– The following routed trace results in no DRC violation
PWR1
TOP
PWR 1
GND
Bottom
5 mil
PWR1
1. Layer Transition
1. Reference change
2. Cross plane split
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© 2014 Cadence Design Systems, Inc..
1. Coplanar reference
DRC Correct or Electrically Correct?
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Impedance mismatch 1
Impedance mismatch 3
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Impedance mismatch 2
Impedance mismatch 4
on
TOP
PWR 1
GND
Radiation
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PWR1
© 2014 Cadence Design Systems, Inc..
Bottom
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5 mil
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PWR1
Radiation
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DRC Correct or Electrically Correct?
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se crosstalk, many follow the ‘3W’ rule – set the
• To minimize
spacing between
critical adjacent traces to 3 times the
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width of the trace
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– The following routed trace results in no DRC violation
5mil
15mil
5mil
‘3W’ rule works for the following structure
5mil 15mil 5mil
3.5mil
No DRC violation
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No Xtalk issue
© 2014 Cadence Design Systems, Inc..
DRC Correct or Electrically Correct?
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• Whatsif the stack-up looks like the following, will ‘3W’ rule
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still work?r
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No DRC violation
Still no Xtalk issue?
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5mil 15mil 5mil
35mil
3.5mil
How do you know?
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© 2014 Cadence Design Systems, Inc..
DRC Correct or Electrically Correct?
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seonly validate MINIMUM, PHYSICAL
• DRCs
requirements
r Uof design constraints
• Do no DRCs mean
sea good, quality design?
• Can PCB designers identify
and
r
Co
address signal quality issues?
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How difficult is it to setup?
Is it easy to use?
Do I have to be an SI expert?
Is it expensive?
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OrCAD Sigrity Technology
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Designers
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© 2014 Cadence Design Systems, Inc..
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Electrical Rule Checks with OrCAD Sigrity ERC
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• ERCs
erbetter than DRCs for signal quality validation
Us setup
• Easy to use, minimal
eidentify
• PCB designers can
r C and address signal quality issues
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– Go beyond MINIMUM, GEOMETRY-BASED constraint validation
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© 2014 Cadence Design Systems, Inc..
OrCAD Sigrity ERC (coming 2015 / 17.0 & QIRs)
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se modeling / setup required
• No complex
• Electricalrchecks
Usinclude
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– SI Metrics (Level 1 & Level 2)
– Differential Pair Serial Link Screening
–
–
–
–
–
–
Trace impedance check
Trace return path check
Via return path check
Trace coupling check
Net coupling check
Additional future checks
• OrCAD FloorPlanner
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On
– Place and route edits only
– Cross-probe (pan / highlight / zoom) between analysis & layout
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OrCAD Sigrity ERC Flow
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Design modification
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Trace Impedance
/ return path
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Coupling / metrics
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Trace Impedance Check
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Visual plot
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• This check helps identify
– Wrong trace width spacing (e.g. diff. pair)
– Plane split cross
– Trace impedance variances
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2
Cross probing
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85Ω
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 Visually or tabular results for trace impedance check
shows trace segment(s) mismatch vs. target impedance
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102Ω
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Trace Impedance Check
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 Cross probing allows issues to be quickly identified
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Trace Impedance Check
GTabular
Results
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• Cross plane split?
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• Any trace segment mismatch? Cross plane split?
• Too much breakout neck length?
• Too much MS/SL routing difference in a group?
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• The same trace length means the same trace delay?
• Routing on MS/SL has different trace delay.
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Trace Coupling Check
GCross
rasprobing helps to easily resolve issues
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Trace Coupling Check
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18X
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0 1 2 3 4 5 6 7
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 Tight coupling pairs
 Max coupling aggressor
 Dangerous vs. safe coupling
 18X ( = 2.81% / 0.156%)
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Trace Reference Check
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 Trace cross layer reference shows the net names for the reference plane
shapes directly above and below the corresponding trace segment
 Trace coplanar reference shows the net names for the reference plane
shapes next to the corresponding trace segment on the same layer
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© 2014 Cadence Design Systems, Inc..
Summary / Benefits
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• ERCs
erbetter than DRCs for signal quality validation
Us
especifically
• OrCAD Sigrity ERC
designed for PCB
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designers leveraging industry-leading
Cadence Sigrity
technology
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• Actionable results to identify and quickly address
On
quality issues
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– Identify issues geometry-based DRCs miss
– Easy to use, minimal setup
– Cross-probing
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© 2014 Cadence Design Systems, Inc..
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©2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence
logo, Sigrity, and OrCAD are registered trademarks and the OrCAD logo is a trademark of
Cadence Design Systems, Inc. in the United States and other countries. All other trademarks
© 2014 Cadence Design Systems,
areInc..
the property of their respective owners.

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