what is trace

Taking Code Trace to the
Next Level
Martin Gisbert
Field Application Engineer
www.iar.com
AGENDA
• What
is Trace?
• Different Trace variants
• Trace probes
• Demo
www.iar.com
AGENDA
• What
is Trace?
• Different Trace variants
• Trace probes
• Demo
www.iar.com
WHAT IS TRACE
•
•
•
Follow your steps vs. (single-)
stepping
Go back in time and evaluate
execution backwards
No gaps
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AGENDA
• What
is Trace?
• Different Trace variants
• Trace probes
• Demo
www.iar.com
OVERVIEW OF TRACE VARIANTS ON
CORTEX-M
•
SWO trace(CM3/4)
• Sampled,
depending on speed of the core and debug probe
• Far from every instruction is traced, ~1 in 8000 instructions
•
ETM trace(optional on CM3/4)
• Dedicated
HW probe with memory onboard -> Investment
• Require several IO pins
• Every instruction traced until the memory full (1M - 4M instructions)
• No speed problem
•
ETB trace (CM0+)
•A
small tracebuffer is located on the device
• Every instruction traced
• Memory in the kB range, instruction clock in the MHz range, two bytes per
instruction -> very limited depth
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6
ARM CORESIGHT OVERVIEW
FPB
DAP
DWT
6 breakpoints
4 watchpoints
PC sampler
ETM trigger
ITM
software trace
32 channels
live
core access
JTAG
I-jet
SWD/SWO
Interrupt trace
CPU statistics
time stamping
ETB
instruction
trace
ITM
Instrumentation Trace
ETM
Embedded Trace Macrocell
ETB
Embedded Trace Buffer
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ETM
instruction trace
trace port
INSTRUMENTATION TRACE MODULE
(ITM)
•
•
Included in Coresight module for ARM Cortex-M3/M4
Low-speed/sampled trace
•
ITM packets are triggered by e.g. interrupts, read/write
access to a variable or if an ITM event is sent actively
•
SWO (single wire output) is a serial high speed signal that
transmits ITM packets
Works with standard debug interface and In-circuit
debugging probe (e.g. IAR Systems I-jet)
•
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ITM/SWO USAGE (EXAMPLE)
Interrupt log window
Data log window
Power debugging
ITM event with line graph
ITM_EVENT(channel_1, my_counter);
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ETM (EMBEDDED TRACE MACROCELL)
•
Separate and optional module on the chip
•
Gives real-time instruction tracing
•
Provides unequaled visibility into processor since every instruction is
traced.
•
Interface at processor speed, so high requirements on the board design
•
Can see without stopping core.
•
Can find “million dollar” bugs that are difficult to find – or impossible any
other way.
•
Allows also hardware code coverage and performance analysis.
•
Can be limited with Trace start/stop breakpoints for efficient use of the
trace buffer
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ETM TRACE FEATURES
Instruction
Profiling
Function
Trace
ETM Trace
Function
Profiler
Code
Coverage
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ETB (EMBEDDED TRACE BUFFER)
•
Low-depth instruction trace
•
Similar functionality as ETM but
•
•
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With the trace buffer on the chip rather than on the trace probe (~2-4
kbyte)
does not require trace pins/probe
AGENDA
• What
is Trace?
• Different Trace variants
• Trace probes
• Demo
www.iar.com
I-JET™
•
Supports ARM7/ARM9/ARM11 and Cortex-M/R/A
cores
•
Hi-speed USB 2.0 interface (480Mbps)
•
Target power of up to 400mA can be supplied
from I-jet with overload protection
•
Target power consumption can be measured with
~200µA resolution at 200kHz
•
JTAG and Serial Wire Debug (SWD) clocks up to
32MHz (no limit on the MCU clock speed)
•
Support for SWO speeds of up to 60MHz
•
Serial Wire Viewer (SWV) with UART and
Manchester encoding
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JTAGjet™-Trace for Cortex-M or ARM
•
Supports Cortex-M/ARM cores equipped with ETM trace logic
•
Up to 200MHz trace clock (400Msample/sec ETM trace
acquisition speed)
•
Auto adjusting timing eliminates problems with data skew
•
Available with 4.5
•
Support for 4, 8 and 16-bit wide trace busses
•
56-bit time stamp with CPU cycle
or 18 MB trace buffer
accuracy for timing analysis
•
Easy access to all ETM modes, triggers and filtering
•
Only one connection to target–both JTAG and trace are taken
from a high-density, 20-pin Cortex header
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AGENDA
• What
is Trace?
• Different Trace variants
• Trace probes
• Demo
www.iar.com
IAR ACADEMY
Book at www.iar.com/academy
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