UART1 Polled Serial I/O

UART1 Polled Serial I/O
The Rx (receive) and Tx (transmit) pins of UART1 (UART one) on the KL46Z can be
connected to pins on the Freedom board’s headers to use with an RS232 interface. The
base address of UART1 in the KL46Z memory map is 0x4006B000. Its registers appear
to the Cortex-M0+ CPU as being at the following addresses.
Register Symbol
UART1_BDH
UART1_BDL
UART1_C1
UART1_C2
UART1_S1
UART1_S2
UART1_C3
UART1_D
UART1_C4
Register Name
Baud Rate High
Baud Rate Low
Control Register 1
Control Register 2
Status Register 1
Status Register 2
Control Register 3
Receive Data Register (Read)/
Transmit Data Register (Write)
Control Register 4
Memory Map Address
0x4006B000
0x4006B001
0x4006B002
0x4006B003
0x4006B004
0x4006B005
0x4006B006
0x4006B007
0x4006B008
Note that both the transmit data register (TDR, write only) and receive data register
(RDR, read only), map to the same UART1_D address. The MKL46Z4.s include file
provided for this course has EQUates for the UART1 register addresses, as named in the
table above, as well as for their offsets from the UART1 base address and for the masks
of each register field.
Using UART1 in a program for polled I/O involves two steps. First, UART1 must be
initialized, which consists of setting the serial communication speed, configuring the
serial communication protocol, and then enabling the UART1’s transmitter and receiver.
This initialization is required only once in the program—typically near its start with other
initialization code. Afterward, UART1 may be used for sending and receiving as many
characters as desired.
SCI initialization
How the UART1 is initialized for baud rate depends on the KL46Z clock configuration.
The MKL46Z4 include file provided for this course has two subroutines that should be
called to configure a 48-MHz core clock for the KL46Z before any UART1 initialization.
(Note that these subroutine calls from main are part of the program template for hardware
programs provided for this course.)
BL
BL
SystemInit
SetClock48MHz
Before UART1 can be initialized, its clock must be enabled. Since it is to be used with
an external device through pins on the Freedom Board, the KL46Z must be configured
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UART1 Polled Serial I/O
Page 2 of 4
for external connection, the pins on the board must be connected, and their clock(s) must
be enabled. For the configuration discussed in class, both pins are part of port E, so the
port E clock must be enabled. Also, port E pin 0 (PTC0) must be connected to the Tx pin
of UART1, and port E pin 1 (PTE1) must be connected to the Rx pin of UART1. The
EQUates and program code that follow are an example of the initialization required for
the UART1 external connection, UART1 module clock, Port E module clock, and Port E
pins.
UART1_EXTERN_MASK_CLEAR
EQU (SIM_SOPT5_UART1ODE_MASK
:OR: SIM_SOPT5_UART1RXSRC_MASK
:OR: SIM_SOPT5_UART1TXSRC_MASK)
UART1CGC_MASK
EQU SIM_SCGC4_UART1_MASK
PORTECGC_MASK
EQU SIM_SCGC5_PORTE_MASK
PIN_MUX_SELECT3
EQU 0x00000300
PTE0_MUX_UART1_TX EQU PIN_MUX_SELECT3
PTE1_MUX_UART1_RX EQU PIN_MUX_SELECT3
SET_PTE0_UART1_TX EQU (PORT_PCR_ISF_MASK
:OR: PTE0_MUX_UART1_TX)
SET_PTE1_UART1_RX EQU (PORT_PCR_ISF_MASK
:OR: PTE1_MUX_UART1_RX)
;Enable external connection for UART1
LDR
Ri,=SIM_SOPT5
LDR
Rj,=UART1_EXTERN_MASK_CLEAR
LDR
Rk,[Ri,#0]
BICS Rk,Rk,Rj
STR
Rk,[Ri,#0]
;Enable clock for UART1 module
LDR
Ri,=SIM_SCGC4
LDR
Rj,=UART1CGC_MASK
LDR
Rk,[Ri,#0]
ORRS Rk,Rk,Rj
STR
Rk,[Ri,#0]
;Enable clock for Port E module
LDR
Ri,=SIM_SCGC5
LDR
Rj,=PORTCCGC_MASK
LDR
Rk,[Ri,#0]
ORRS Rk,Rk,Rj
STR
Rk,[Ri,#0]
;Connect UART1 Tx to Port E pin 0 (PTE0)
LDR
Ri,=PORTE_PCR0
LDR
Rj,=SET_PTE0_UART1_TX
STR
Rj,[Ri,#0]
;Connect UART1 Rx to Port E pin 1 (PTE1)
LDR
Ri,=PORTC_PCR4
LDR
Rj,=SET_PTE1_UART1_RX
STR
Rj,[Ri,#0]
UART1 Polled Serial I/O
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These internal KL46Z connections make UART1 Rx available on pin 20 of the Freedom
Board’s connector J2 and UART1 Tx available on pin 18 of connector J2, because those
pins connect to KL46Z port E pins 1 and 0 (PTE1 and PTE0), respectively. To work
with a terminal using a 5-V serial connection, these 3.3-V digital signals must be
conditioned by a serial adapter. The course hardware kit contains a serial USB adapter.
The figure below shows the required wiring between the Freedom Board and the serial
adapter..
RX 5
TX 4
GND 1
UART USB
Adapter
J2.18 PTE0 (UART1_Tx)
J2.20 PTE1 (UART1_Rx)
J9.14 GND
Freescale
FRDM-KL46Z
Freedom Board KL46Z connections to serial adapter
In addition to the initialization to make the UART1 Rx and Tx signals available through
Port E, UART1 needs to be configured for the proper serial rate and protocol to
communicate with the connected PC through PuTTY (or another serial terminal
program). The 13-bit value in the baud rate registers determines the timing, control
register 1 bit 4 (M) sets the character data bits, and control register 1 bit 1 (PE) sets the
parity. If PuTTY is set for 9600 baud with 8 data bits, no parity bit, and 1 stop bit,
(which is the default setting), control register 1 needs to be set to 0x00, (0 for both M and
PE). Control registers 3 and 4 also should be set to 0x00. After the serial baud rate and
protocol are set in these control registers, the UART1’s receiver and transmitter need to
be enabled. Control register 2 bit 3 (TE) and bit 2 (RE) enable the transmitter and
receiver, respectively, so control register 2 needs to be set to 0x0C, (which also disables
all transmitter and receiver interrupts). The EQUates and program code that follow are
an example of the initialization required for UART1 operation.
UART_BDH_9600
UART_BDL_9600
UART_C1_8N1
UART_C2_T_R:
EQU
EQU
EQU
EQU
0x00
156
0x00
(UART_C2_TE_MASK :OR:
UART_C2_RE_MASK)
UART_C3_NO_TXINV EQU 0x00
UART_C4_NO_DMA
EQU 0x00
UART_S2_NO_RXINV_BRK10_NO_LBKDETECT
EQU 0x00
LDR
Ri,=UART1_BASE
MOVS Rj,#UART_BDH_9600
STRB Rj,[Ri,#UART_BDH_OFFSET]
MOVS Rj,#UART_BDL_9600
STRB Rj,[Ri,#UART_BDL_OFFSET]
MOVS Rj,#UART_C1_8N1
STRB Rj,[Ri,#UART_C1_OFFSET]
MOVS Rj,#UART_C3_NO_TXINV
STRB Rj,[Ri,#UART_C3_OFFSET]
MOVS Rj,#UART_C4_NO_DMA
STRB Rj,[Ri,#UART_C4_OFFSET]
MOVS Rj,#UART_S2_NO_RXINV_BRK10_NO_LBKDETECT
UART1 Polled Serial I/O
STRB
MOVS
STRB
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Rj,[Ri,#UART_S2_OFFSET]
Rj,#UART_C2_T_R
Rj,[Ri,#UART_C2_OFFSET]
UART1 polled transmit and receive
Once a program has initialized UART1 for the proper serial baud rate and protocol and
has enabled it to transmit and receive, the program may use UART1 to send and receive
data. The following examples use Ri for character I/O.
Transmit. A polled transmit (i.e., send character) polls UART1’s status register 1 for the
transmit data register empty (TDRE) condition. If TDRE = 1, a byte may be transmitted
(i.e., sent); otherwise, a byte may not yet be transmitted, and the status register must be
polled until TDRE = 1. The TDRE condition flag is bit 7 of UART1 status register 1.
The MKL46Z4.s include file provided for this course has a UART_S1_TDRE_MASK
EQUate that defines a mask with a 1 in the TDRE position. The following code
implements a polled transmit for a single character—the basis for a “PutChar” operation.
;Poll TDRE until UART1 ready to transmit
LDR
Rj,=UART1_BASE
MOVS Rk,#UART_S1_TDRE_MASK
PollTx: LDRB Rm,[Rj,#UART_S1_OFFSET]
ANDS Rm,Rm,Rk
BEQ
PollTx
;Transmit character in Ri
STRB Ri,[Rj,#UART_D_OFFSET]
Receive. Similarly, a polled receive (i.e., get character) polls UART1’s status register 1
for the receive data register full (RDRF) condition. If RDRF = 1, a byte has been
received through the serial connection and is ready to be read (i.e., received by the
KL46Z); otherwise, a byte has not yet been received, and the status register must be
polled until RDRF = 1. The RDRF condition flag is bit 5 of UART1 status register 1.
The MKL46Z4.s include file provided for this course has a UART_S1_RDRF_MASK
EQUate that defines a mask with a 1 in the RDRF position. The following code
implements a polled receive for a single character—the basis for a “GetChar” operation.
;Poll RDRF until UART1 ready to receive
LDR
Rj,=UART1_BASE
MOVS Rk,#UART_S1_RDRF_MASK
PollRx: LDRB Rm,[Rj,#UART_S1_OFFSET]
ANDS Rm,Rm,Rk
BEQ
PollRx
;Receive character in Ri
LDRB Ri,[Rj,#UART_D_OFFSET]

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