Investigation of ZEP 520A behavior in process of submicron GaN

Investigation of ZEP 520A behavior in process of submicron GaN HEMTs
slanted gate fabrication
K. Y. Osipov*, W. John, N. Kemf, S. A. Chevtchenko, P. Kurpas, M. Matalla, O. Krüger, and
J. Würfl
Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH),
Gustav-Kirchhoff-Str. 4, 12489 Berlin, Germany
* E-mail: [email protected]
ABSTRACT
In the present work, detailed investigations of ZEP 520A
e-beam resist behavior during SiNx masking and
consequent plasma etching of gate trenches were
performed. Influence of resist reflow temperature and
time on the final shape and quality of the trenches is
presented. Furthermore, influences of base plate
temperature during plasma etching on the trench quality
and etch process selectivity are discussed. Consequently,
an optimization of wafer cooling in plasma etching
process was performed in order to avoid resist mask
overheating.
1. INTRODUCTION
The formation of short slanted gates (100 nm and shorter)
is an essential part of high frequency GaN HEMTs
fabrication technology. For operation frequencies above
30 GHz, a gate length of about 100 nm is required. One
of the possible ways to create short slanted gates is to use
thermally reflowed e-beam resist as an etch mask for the
gate trench formation [1]. In this paper we have
investigated the behavior of ZEP 520A e-beam resist
during thermal reflow and plasma etching processes. This
type of resist is well known for its high dry etching
stability. Therefore, it is ideally suited for the fabrication
of gates embedded in SiNx. During a thermal reflow of
developed ZEP 520A features shrink in dimensions and
provide rounded resist edge profiles [2], which allows
fabrication of narrow and slanted gate trenches. However,
during plasma etching, the resist mask undergoes
significant heating, which can cause resist deformation
and increase of resist etch rate with consequent decrease
of process selectivity. In the present work the influence of
different resist reflow and plasma etching conditions on
the final shape and the quality of the bottom and
sidewalls of gate trenches in SiNx is analyzed.
65 μC/cm². Reflow of the resist was performed on a
calibrated hotplate at different temperatures and for
various time intervals. After reflow, samples were etched
using a Sentech SI500 ICP tool. Size and profile of trench
openings in SiNx were analyzed using scanning electron
microscopy (SEM).
3. RESULTS AND DISCUSSION
3.1. ZEP 520A thermal reflow regimes
Fig. 1 shows the dependence of the sidewall trench slope
in SiNx on the resist reflow temperature and time. As can
be seen, with increasing of reflow temperature the
sidewall slope of the trench is reduced. With respect to
reflow time a similar tendency exists, longer reflow
causes more gradual sidewalls. This provides the
possibility of obtaining the same trench sidewall slope
using proper combinations of reflow temperature and
time. In order to check trench sidewall quality obtained at
different reflow temperatures, top-view SEM inspection
of etched samples was performed. Fig. 2 shows SEM
images of samples reflowed at different temperatures for
20 min and then etched. During the dry etch process the
resist profile has been transferred to the SiNx film. It is
clearly visible that, compared to masks reflowed at lower
temperatures, masks reflowed at higher temperatures give
relatively rough trench sidewalls. To get information on
the effect of reflow time a batch of samples has been
fabricated where the reflow process has been terminated
after 5 minutes (instead of 20 minutes previously). The
reflow temperatures have been kept the same. Fig. 3
shows the quality of the resulting sidewalls after reflow at
2. EXPERIMENT
All experiments were performed using 4 inch s.i. GaAs
wafers. All wafers were passivated with 100 nm thick
SiNx films deposited at 345 °C using a Sentech SI500D
PECVD tool. The ZEP 520A (Nippon Zeon) co-polymer
resist was 50% diluted, spun at 2000 rpm and
subsequently baked for 3 min at 115 °C, resulting in a
final thickness of ~210 nm. Exposure was performed
using a Vistec SB251 electron beam lithography tool with
an acceleration voltage of 50 kV and a dose of
Figure 1 – Dependence of trench sidewall slope on resist reflow
temperature and time.
WOCSDICE-2014
150 oC and 160 oC. As can be seen from the pictures, the
trench sidewall roughness is similar to that of samples
reflowed during 20 minutes at the same temperatures (see
Fig. 2). As no significant difference between samples
reflowed during 5 min and 20 min at the same
temperatures was observed, it can be concluded, that
sidewall roughness depends only on reflow temperature,
but is fairly independent on reflow time. In order to
maintain a smooth trench sidewall profile it is therefore
preferable to use low resist reflow temperatures. For
controlling the sidewall angle it is preferable to stick with
the lower reflow temperature but increase the reflow
time.
150 oC
160 oC
155 oC
165 oC
Figure 2 – Trenches in SiNx etched through masks reflowed at
different temperatures for 20 min.
150 oC
160 oC
Figure 3 – SEM images of trenches in SiNx etched using resist
mask reflow at 150 oC and 160 oC for 5 min.
10 oC
30 oC
between wafer and cooled carrier, and therefore can cause
local overheating of the wafer in the case of a large heat
flux provided by the plasma. Wafer etching tests in this
regime have shown, that due to overheating during the
etch process an additional in-situ reflow of the resist
mask occurs. This in-situ reflow causes high roughness of
trench sidewalls, uncontrollable feature shrinking and
significant increase of the resist etch rate. The second
regime is a direct cooling. In this case the wafer is
clamped inside the carrier and the cooling agent directly
contacts the wafer’s back, providing reliable thermal
contact. Applying the direct cooling did not show any
signs overheating. However, when the temperature of the
cooling agent was decreased down to 10°C, traces of
contamination were observed at the bottom of the
trenches (Fig. 4). Experimentally it has been found that
these traces disappear when etching is performed using
cooling agent temperature 30 oC. This result shows that
the observed contaminations most probably are related to
redeposition of etched SiNx and/or resist mask material.
With increase of sample temperature redeposited particles
do not stick to the surface as they have enough energy for
evaporation and subsequent removal from the chamber.
As can be seen from the results of the experiment, proper
etching of trenches is possible only in a narrow
temperature range. Too high and too low temperatures
during trench etching cause undesirable effects, which
deteriorate the trench quality.
4. CONCLUSIONS
The general trends of influence of ZEP 520A e-beam
resist thermal reflow regimes on the quality of trenches in
SiNx have been presented. It was shown that the reflow
temperature has a significant influence on subsequent
trench quality. The use of low temperatures is preferable
in terms of trench sidewall quality. In cases when it is
necessary to decrease feature size or/and sidewall slope
angle, the increase of reflow process time rather than
increase of reflow temperature is recommended.
Significant influence of the wafer temperature during the
etch process on the final trench quality has been shown. It
has been found that proper wafer cooling down to
temperatures of about 30°C (for the actual plasma etching
conditions) prevents resist mask overheating and
redeposition of contaminating particles in the trench
bottom.
5. REFERENCES
Figure 4 – SEM images of trenches in SiNx etched at different
wafer cooling conditions.
3.2. Optimization of cooling conditions during the
plasma etch step
The plasma etching equipment used in the presented
experiments has two different regimes of wafers cooling
during the etch process. The first regime is indirect
cooling – i.e. the wafer lies on a top of the cooled carrier.
This regime cannot provide a reliable thermal contact
[1] K. Y. Osipov, W. John, N. Kemf, S. A. Chevtchenko, P.
Kurpas, M. Matalla, O. Krüger, and J. Würfl, “Fabrication
technology of GaN/AlGaN HEMT slanted sidewall gates
using thermally reflowed ZEP resist and CHF3/SF6 plasma
etching”, CS Mantech Conf., 2013.
[2] B. P. Downey, D. J. Meyer, R. Bass, D. S. Katzer and S. C.
Binari, Thermally reflowed ZEP 520A for gate length
reduction and profile rounding in T-gate fabrication, J.
Vac. Sci. Technol. B, Vol. 30(5), 051603-1 – 051603-5,
Sept/Oct 2012.
WOCSDICE-2014

Download Report